source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem8k8.xise @ 137

Last change on this file since 137 was 137, checked in by rolagamo, 10 years ago
File size: 4.7 KB
Line 
1<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4  <header>
5    <!-- ISE source project file created by Project Navigator.             -->
6    <!--                                                                   -->
7    <!-- This file contains project source information including a list of -->
8    <!-- project source files, project and process properties.  This file, -->
9    <!-- along with the project source files, is sufficient to open and    -->
10    <!-- implement in ISE Project Navigator.                               -->
11    <!--                                                                   -->
12    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
13  </header>
14
15  <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/>
16
17  <files>
18    <file xil_pn:name="mem8k8.ngc" xil_pn:type="FILE_NGC">
19      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
20      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
21    </file>
22    <file xil_pn:name="mem8k8.vhd" xil_pn:type="FILE_VHDL">
23      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
24      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
25      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
26      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
27      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
28    </file>
29  </files>
30
31  <properties>
32    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
33    <property xil_pn:name="Device" xil_pn:value="xc7a100t" xil_pn:valueState="non-default"/>
34    <property xil_pn:name="Device Family" xil_pn:value="Artix7" xil_pn:valueState="non-default"/>
35    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
36    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mem8k8|mem8k8_a" xil_pn:valueState="non-default"/>
37    <property xil_pn:name="Implementation Top File" xil_pn:value="mem8k8.vhd" xil_pn:valueState="non-default"/>
38    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mem8k8" xil_pn:valueState="non-default"/>
39    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/>
40    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
41    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
42    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
43    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
44    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
45    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
46    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
47    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
48    <!--                                                                                  -->
49    <!-- The following properties are for internal use only. These should not be modified.-->
50    <!--                                                                                  -->
51    <property xil_pn:name="PROP_DesignName" xil_pn:value="mem8k8" xil_pn:valueState="non-default"/>
52    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="artix7" xil_pn:valueState="default"/>
53    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-09T15:44:54" xil_pn:valueState="non-default"/>
54    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0A14F46BA6CA40C6870EDAC9BBAA198D" xil_pn:valueState="non-default"/>
55    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
56    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
57  </properties>
58
59  <bindings/>
60
61  <libraries/>
62
63  <autoManagedFiles>
64    <!-- The following files are identified by `include statements in verilog -->
65    <!-- source files and are automatically managed by Project Navigator.     -->
66    <!--                                                                      -->
67    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
68    <!-- project is analyzed based on files automatically identified as       -->
69    <!-- include files.                                                       -->
70  </autoManagedFiles>
71
72</project>
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