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2 | -------------------------------------------------------------------------------- |
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3 | -- |
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4 | -- BLK MEM GEN v6.2 Core - Top-level wrapper |
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5 | -- |
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6 | -------------------------------------------------------------------------------- |
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7 | -- |
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8 | -- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. |
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9 | -- |
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10 | -- This file contains confidential and proprietary information |
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11 | -- of Xilinx, Inc. and is protected under U.S. and |
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12 | -- international copyright and other intellectual property |
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13 | -- laws. |
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14 | -- |
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15 | -- DISCLAIMER |
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16 | -- This disclaimer is not a license and does not grant any |
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17 | -- rights to the materials distributed herewith. Except as |
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18 | -- otherwise provided in a valid license issued to you by |
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19 | -- Xilinx, and to the maximum extent permitted by applicable |
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20 | -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
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21 | -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES |
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22 | -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
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23 | -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
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24 | -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
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25 | -- (2) Xilinx shall not be liable (whether in contract or tort, |
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26 | -- including negligence, or under any other theory of |
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27 | -- liability) for any loss or damage of any kind or nature |
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28 | -- related to, arising under or in connection with these |
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29 | -- materials, including for any direct, or any indirect, |
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30 | -- special, incidental, or consequential loss or damage |
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31 | -- (including loss of data, profits, goodwill, or any type of |
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32 | -- loss or damage suffered as a result of any action brought |
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33 | -- by a third party) even if such damage or loss was |
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34 | -- reasonably foreseeable or Xilinx had been advised of the |
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35 | -- possibility of the same. |
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36 | -- |
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37 | -- CRITICAL APPLICATIONS |
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38 | -- Xilinx products are not designed or intended to be fail- |
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39 | -- safe, or for use in any application requiring fail-safe |
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40 | -- performance, such as life-support or safety devices or |
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41 | -- systems, Class III medical devices, nuclear facilities, |
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42 | -- applications related to the deployment of airbags, or any |
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43 | -- other applications that could lead to death, personal |
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44 | -- injury, or severe property or environmental damage |
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45 | -- (individually and collectively, "Critical |
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46 | -- Applications"). Customer assumes the sole risk and |
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47 | -- liability of any use of Xilinx products in Critical |
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48 | -- Applications, subject only to applicable laws and |
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49 | -- regulations governing limitations on product liability. |
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50 | -- |
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51 | -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
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52 | -- PART OF THIS FILE AT ALL TIMES. |
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53 | -- |
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54 | -------------------------------------------------------------------------------- |
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55 | -- |
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56 | -- Filename: bmg_wrapper.vhd |
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57 | -- |
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58 | -- Description: |
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59 | -- This is the top-level BMG wrapper (over BMG core). |
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60 | -- |
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61 | -------------------------------------------------------------------------------- |
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62 | -- Author: IP Solutions Division |
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63 | -- |
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64 | -- History: August 31, 2005 - First Release |
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65 | -------------------------------------------------------------------------------- |
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66 | -- |
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67 | -- Configured Core Parameter Values: |
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68 | -- (Refer to the SIM Parameters table in the datasheet for more information on |
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69 | -- the these parameters.) |
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70 | -- C_FAMILY : artix7 |
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71 | -- C_XDEVICEFAMILY : artix7 |
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72 | -- C_INTERFACE_TYPE : 0 |
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73 | -- C_AXI_TYPE : 1 |
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74 | -- C_AXI_SLAVE_TYPE : 0 |
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75 | -- C_AXI_ID_WIDTH : 4 |
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76 | -- C_MEM_TYPE : 1 |
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77 | -- C_BYTE_SIZE : 9 |
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78 | -- C_ALGORITHM : 1 |
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79 | -- C_PRIM_TYPE : 1 |
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80 | -- C_LOAD_INIT_FILE : 0 |
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81 | -- C_INIT_FILE_NAME : no_coe_file_loaded |
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82 | -- C_USE_DEFAULT_DATA : 0 |
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83 | -- C_DEFAULT_DATA : 0 |
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84 | -- C_RST_TYPE : SYNC |
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85 | -- C_HAS_RSTA : 0 |
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86 | -- C_RST_PRIORITY_A : CE |
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87 | -- C_RSTRAM_A : 0 |
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88 | -- C_INITA_VAL : 0 |
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89 | -- C_HAS_ENA : 1 |
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90 | -- C_HAS_REGCEA : 0 |
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91 | -- C_USE_BYTE_WEA : 0 |
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92 | -- C_WEA_WIDTH : 1 |
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93 | -- C_WRITE_MODE_A : WRITE_FIRST |
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94 | -- C_WRITE_WIDTH_A : 8 |
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95 | -- C_READ_WIDTH_A : 8 |
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96 | -- C_WRITE_DEPTH_A : 8191 |
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97 | -- C_READ_DEPTH_A : 8191 |
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98 | -- C_ADDRA_WIDTH : 13 |
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99 | -- C_HAS_RSTB : 0 |
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100 | -- C_RST_PRIORITY_B : CE |
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101 | -- C_RSTRAM_B : 0 |
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102 | -- C_INITB_VAL : 0 |
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103 | -- C_HAS_ENB : 1 |
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104 | -- C_HAS_REGCEB : 0 |
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105 | -- C_USE_BYTE_WEB : 0 |
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106 | -- C_WEB_WIDTH : 1 |
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107 | -- C_WRITE_MODE_B : WRITE_FIRST |
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108 | -- C_WRITE_WIDTH_B : 8 |
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109 | -- C_READ_WIDTH_B : 8 |
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110 | -- C_WRITE_DEPTH_B : 8191 |
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111 | -- C_READ_DEPTH_B : 8191 |
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112 | -- C_ADDRB_WIDTH : 13 |
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113 | -- C_HAS_MEM_OUTPUT_REGS_A : 0 |
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114 | -- C_HAS_MEM_OUTPUT_REGS_B : 0 |
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115 | -- C_HAS_MUX_OUTPUT_REGS_A : 0 |
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116 | -- C_HAS_MUX_OUTPUT_REGS_B : 0 |
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117 | -- C_HAS_SOFTECC_INPUT_REGS_A : 0 |
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118 | -- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 |
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119 | -- C_MUX_PIPELINE_STAGES : 0 |
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120 | -- C_USE_ECC : 0 |
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121 | -- C_USE_SOFTECC : 0 |
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122 | -- C_HAS_INJECTERR : 0 |
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123 | -- C_SIM_COLLISION_CHECK : ALL |
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124 | -- C_COMMON_CLK : 0 |
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125 | -- C_DISABLE_WARN_BHV_COLL : 0 |
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126 | -- C_DISABLE_WARN_BHV_RANGE : 0 |
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127 | |
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128 | -------------------------------------------------------------------------------- |
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129 | -- Library Declarations |
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130 | -------------------------------------------------------------------------------- |
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131 | |
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132 | LIBRARY IEEE; |
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133 | USE IEEE.STD_LOGIC_1164.ALL; |
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134 | USE IEEE.STD_LOGIC_ARITH.ALL; |
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135 | USE IEEE.STD_LOGIC_UNSIGNED.ALL; |
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136 | |
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137 | LIBRARY UNISIM; |
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138 | USE UNISIM.VCOMPONENTS.ALL; |
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139 | |
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140 | -------------------------------------------------------------------------------- |
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141 | -- Entity Declaration |
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142 | -------------------------------------------------------------------------------- |
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143 | ENTITY bmg_wrapper IS |
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144 | PORT ( |
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145 | --Port A |
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146 | CLKA : IN STD_LOGIC; |
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147 | RSTA : IN STD_LOGIC; --opt port |
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148 | ENA : IN STD_LOGIC; --optional port |
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149 | REGCEA : IN STD_LOGIC; --optional port |
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150 | WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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151 | ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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152 | DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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153 | DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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154 | |
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155 | --Port B |
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156 | CLKB : IN STD_LOGIC; |
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157 | RSTB : IN STD_LOGIC; --opt port |
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158 | ENB : IN STD_LOGIC; --optional port |
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159 | REGCEB : IN STD_LOGIC; --optional port |
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160 | WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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161 | ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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162 | DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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163 | DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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164 | |
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165 | --ECC |
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166 | INJECTSBITERR : IN STD_LOGIC; --optional port |
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167 | INJECTDBITERR : IN STD_LOGIC; --optional port |
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168 | SBITERR : OUT STD_LOGIC; --optional port |
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169 | DBITERR : OUT STD_LOGIC; --optional port |
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170 | RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port |
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171 | -- AXI BMG Input and Output Port Declarations |
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172 | |
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173 | -- AXI Global Signals |
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174 | S_ACLK : IN STD_LOGIC; |
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175 | S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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176 | S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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177 | S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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178 | S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
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179 | S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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180 | S_AXI_AWVALID : IN STD_LOGIC; |
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181 | S_AXI_AWREADY : OUT STD_LOGIC; |
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182 | S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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183 | S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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184 | S_AXI_WLAST : IN STD_LOGIC; |
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185 | S_AXI_WVALID : IN STD_LOGIC; |
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186 | S_AXI_WREADY : OUT STD_LOGIC; |
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187 | S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); |
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188 | S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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189 | S_AXI_BVALID : OUT STD_LOGIC; |
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190 | S_AXI_BREADY : IN STD_LOGIC; |
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191 | |
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192 | -- AXI Full/Lite Slave Read (Write side) |
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193 | S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
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194 | S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
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195 | S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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196 | S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); |
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197 | S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); |
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198 | S_AXI_ARVALID : IN STD_LOGIC; |
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199 | S_AXI_ARREADY : OUT STD_LOGIC; |
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200 | S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); |
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201 | S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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202 | S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); |
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203 | S_AXI_RLAST : OUT STD_LOGIC; |
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204 | S_AXI_RVALID : OUT STD_LOGIC; |
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205 | S_AXI_RREADY : IN STD_LOGIC; |
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206 | |
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207 | -- AXI Full/Lite Sideband Signals |
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208 | S_AXI_INJECTSBITERR : IN STD_LOGIC; |
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209 | S_AXI_INJECTDBITERR : IN STD_LOGIC; |
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210 | S_AXI_SBITERR : OUT STD_LOGIC; |
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211 | S_AXI_DBITERR : OUT STD_LOGIC; |
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212 | S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); |
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213 | S_ARESETN : IN STD_LOGIC |
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214 | |
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215 | |
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216 | ); |
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217 | |
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218 | END bmg_wrapper; |
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219 | |
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220 | |
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221 | ARCHITECTURE xilinx OF bmg_wrapper IS |
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222 | |
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223 | COMPONENT mem8k8_top IS |
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224 | PORT ( |
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225 | --Port A |
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226 | ENA : IN STD_LOGIC; --opt port |
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227 | |
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228 | WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); |
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229 | ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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230 | |
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231 | DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); |
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232 | |
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233 | |
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234 | CLKA : IN STD_LOGIC; |
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235 | |
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236 | |
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237 | --Port B |
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238 | ENB : IN STD_LOGIC; --opt port |
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239 | ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); |
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240 | DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
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241 | CLKB : IN STD_LOGIC |
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242 | |
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243 | |
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244 | ); |
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245 | END COMPONENT; |
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246 | |
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247 | BEGIN |
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248 | |
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249 | bmg0 : mem8k8_top |
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250 | PORT MAP ( |
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251 | --Port A |
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252 | ENA => ENA, |
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253 | |
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254 | WEA => WEA, |
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255 | ADDRA => ADDRA, |
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256 | |
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257 | DINA => DINA, |
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258 | |
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259 | CLKA => CLKA, |
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260 | |
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261 | --Port B |
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262 | ENB => ENB, |
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263 | ADDRB => ADDRB, |
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264 | DOUTB => DOUTB, |
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265 | CLKB => CLKB |
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266 | |
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267 | |
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268 | ); |
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269 | END xilinx; |
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