[115] | 1 | # (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved. |
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| 2 | # |
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| 3 | # This file contains confidential and proprietary information |
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| 4 | # of Xilinx, Inc. and is protected under U.S. and |
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| 5 | # international copyright and other intellectual property |
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| 6 | # laws. |
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| 7 | # |
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| 8 | # DISCLAIMER |
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| 10 | # rights to the materials distributed herewith. Except as |
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| 11 | # otherwise provided in a valid license issued to you by |
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| 12 | # Xilinx, and to the maximum extent permitted by applicable |
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| 13 | # law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND |
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| 15 | # AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING |
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| 16 | # BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- |
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| 17 | # INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and |
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| 28 | # possibility of the same. |
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| 29 | # |
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| 30 | # CRITICAL APPLICATIONS |
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| 31 | # Xilinx products are not designed or intended to be fail- |
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| 38 | # (individually and collectively, "Critical |
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| 39 | # Applications"). Customer assumes the sole risk and |
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| 40 | # liability of any use of Xilinx products in Critical |
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| 41 | # Applications, subject only to applicable laws and |
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| 42 | # regulations governing limitations on product liability. |
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| 43 | # |
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| 44 | # THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS |
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| 45 | # PART OF THIS FILE AT ALL TIMES. |
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| 46 | |
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| 47 | |
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| 48 | set device xc6slx45csg324-3 |
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| 49 | set projName mem8k8 |
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| 50 | set design mem8k8 |
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| 51 | set projDir [file dirname [info script]] |
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| 52 | create_project $projName $projDir/results/$projName -part $device -force |
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| 53 | set_property design_mode RTL [current_fileset -srcset] |
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| 54 | set top_module mem8k8_top |
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| 55 | add_files -norecurse {../../example_design/mem8k8_top.vhd} |
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| 56 | add_files -norecurse {./mem8k8.edf} |
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| 57 | import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/mem8k8_top.xdc} |
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| 58 | set_property top mem8k8_top [get_property srcset [current_run]] |
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| 59 | synth_design |
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| 60 | opt_design |
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| 61 | place_design |
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| 62 | route_design |
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| 63 | set_param sta.dlyMediator true |
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| 64 | write_sdf -rename_top_module mem8k8_top -file routed.sdf |
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| 65 | write_verilog -nolib -mode sim -sdf_anno false -rename_top_module mem8k8_top routed.vhd |
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| 66 | report_timing -nworst 30 -path_type full -file routed.twr |
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| 67 | report_drc -file routed.drc |
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| 68 | #write_bitstream |
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