1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?> |
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2 | <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> |
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3 | |
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4 | <header> |
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5 | <!-- ISE source project file created by Project Navigator. --> |
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6 | <!-- --> |
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7 | <!-- This file contains project source information including a list of --> |
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8 | <!-- project source files, project and process properties. This file, --> |
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9 | <!-- along with the project source files, is sufficient to open and --> |
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10 | <!-- implement in ISE Project Navigator. --> |
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11 | <!-- --> |
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12 | <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
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13 | </header> |
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14 | |
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15 | <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/> |
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16 | |
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17 | <files> |
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18 | <file xil_pn:name="mem_4k8.ngc" xil_pn:type="FILE_NGC"> |
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19 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> |
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20 | <association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
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21 | </file> |
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22 | <file xil_pn:name="mem_4k8.vhd" xil_pn:type="FILE_VHDL"> |
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23 | <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> |
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24 | <association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
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25 | <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/> |
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26 | <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/> |
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27 | <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/> |
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28 | </file> |
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29 | </files> |
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30 | |
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31 | <properties> |
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32 | <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/> |
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33 | <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/> |
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34 | <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/> |
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35 | <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/> |
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36 | <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|mem_4k8|mem_4k8_a" xil_pn:valueState="non-default"/> |
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37 | <property xil_pn:name="Implementation Top File" xil_pn:value="mem_4k8.vhd" xil_pn:valueState="non-default"/> |
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38 | <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/mem_4k8" xil_pn:valueState="non-default"/> |
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39 | <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/> |
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40 | <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/> |
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41 | <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/> |
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42 | <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/> |
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43 | <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> |
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44 | <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> |
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45 | <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> |
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46 | <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> |
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47 | <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> |
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48 | <!-- --> |
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49 | <!-- The following properties are for internal use only. These should not be modified.--> |
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50 | <!-- --> |
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51 | <property xil_pn:name="PROP_DesignName" xil_pn:value="mem_4k8" xil_pn:valueState="non-default"/> |
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52 | <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> |
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53 | <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-03-03T08:17:20" xil_pn:valueState="non-default"/> |
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54 | <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C0D96C8DEC5F479F8D5451528E624BEE" xil_pn:valueState="non-default"/> |
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55 | <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> |
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56 | <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> |
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57 | </properties> |
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58 | |
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59 | <bindings/> |
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60 | |
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61 | <libraries/> |
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62 | |
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63 | <autoManagedFiles> |
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64 | <!-- The following files are identified by `include statements in verilog --> |
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65 | <!-- source files and are automatically managed by Project Navigator. --> |
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66 | <!-- --> |
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67 | <!-- Do not hand-edit this section, as it will be overwritten when the --> |
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68 | <!-- project is analyzed based on files automatically identified as --> |
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69 | <!-- include files. --> |
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70 | </autoManagedFiles> |
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71 | |
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72 | </project> |
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