source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_4k8_ste/implement/implement.bat @ 115

rem Clean up the results directory
rmdir /S /Q results
mkdir results

rem Synthesize the VHDL Wrapper Files


echo 'Synthesizing example design with XST';
xst -ifn xst.scr
copy mem_4k8_top.ngc .\results\


rem Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
copy ..\..\mem_4k8.ngc results\


rem  Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\example_design\mem_4k8_top.ucf results\

cd results

echo 'Running ngdbuild'
ngdbuild -p xc6slx45-csg324-3 mem_4k8_top

echo 'Running map'
map mem_4k8_top -o mapped.ncd -pr i

echo 'Running par'
par mapped.ncd routed.ncd

echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed

echo 'Running design through bitgen'
bitgen -w routed

echo 'Running netgen to create gate level VHDL model'
netgen -ofmt vhdl -sim -tm mem_4k8_top -pcf mapped.pcf -w routed.ncd routed.vhd