Last change
on this file since 127 was
115,
checked in by rolagamo, 10 years ago
|
Ajout des Cores utilisés dans le projet
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File size:
1.0 KB
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Line | |
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1 | #!/bin/sh |
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2 | |
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3 | # Clean up the results directory |
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4 | rm -rf results |
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5 | mkdir results |
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6 | |
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7 | #Synthesize the Wrapper Files |
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8 | echo 'Synthesizing XST wrapper file (core_top.vhd) with XST'; |
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9 | echo 'Synthesizing example design with XST'; |
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10 | xst -ifn xst.scr |
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11 | cp mem_4k8_top.ngc ./results/ |
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12 | |
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13 | |
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14 | # Copy the netlist generated by Coregen |
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15 | echo 'Copying files from the netlist directory to the results directory' |
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16 | cp ../../mem_4k8.ngc results/ |
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17 | |
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18 | # Copy the constraints files generated by Coregen |
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19 | echo 'Copying files from constraints directory to results directory' |
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20 | cp ../example_design/mem_4k8_top.ucf results/ |
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21 | |
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22 | cd results |
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23 | |
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24 | echo 'Running ngdbuild' |
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25 | ngdbuild -p xc6slx45-csg324-3 mem_4k8_top |
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26 | |
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27 | echo 'Running map' |
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28 | map mem_4k8_top -o mapped.ncd -pr i |
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29 | |
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30 | echo 'Running par' |
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31 | par mapped.ncd routed.ncd |
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32 | |
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33 | echo 'Running trce' |
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34 | trce -e 10 routed.ncd mapped.pcf -o routed |
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35 | |
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36 | echo 'Running design through bitgen' |
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37 | bitgen -w routed |
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38 | |
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39 | echo 'Running netgen to create gate level VHDL model' |
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40 | netgen -ofmt vhdl -sim -tm mem_4k8_top -pcf mapped.pcf -w routed.ncd routed.vhd |
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