Last change
on this file since 116 was
115,
checked in by rolagamo, 11 years ago
|
Ajout des Cores utilisés dans le projet
|
File size:
519 bytes
|
Rev | Line | |
---|
[115] | 1 | # Date: Sun Mar 02 19:33:45 2014 |
---|
| 2 | |
---|
| 3 | SET addpads = false |
---|
| 4 | SET asysymbol = true |
---|
| 5 | SET busformat = BusFormatAngleBracketNotRipped |
---|
| 6 | SET createndf = false |
---|
| 7 | SET designentry = VHDL |
---|
| 8 | SET device = xc6slx45 |
---|
| 9 | SET devicefamily = spartan6 |
---|
| 10 | SET flowvendor = Other |
---|
| 11 | SET formalverification = false |
---|
| 12 | SET foundationsym = false |
---|
| 13 | SET implementationfiletype = Ngc |
---|
| 14 | SET package = csg324 |
---|
| 15 | SET removerpms = false |
---|
| 16 | SET simulationfiles = Behavioral |
---|
| 17 | SET speedgrade = -3 |
---|
| 18 | SET verilogsim = false |
---|
| 19 | SET vhdlsim = true |
---|
| 20 | SET workingdirectory = .\tmp\ |
---|
| 21 | |
---|
| 22 | # CRC: 1242dfe7 |
---|
Note: See
TracBrowser
for help on using the repository browser.