Last change
on this file since 116 was
115,
checked in by rolagamo, 11 years ago
|
Ajout des Cores utilisés dans le projet
|
File size:
519 bytes
|
Line | |
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1 | # Date: Sun Mar 02 19:33:45 2014 |
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2 | |
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3 | SET addpads = false |
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4 | SET asysymbol = true |
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5 | SET busformat = BusFormatAngleBracketNotRipped |
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6 | SET createndf = false |
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7 | SET designentry = VHDL |
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8 | SET device = xc6slx45 |
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9 | SET devicefamily = spartan6 |
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10 | SET flowvendor = Other |
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11 | SET formalverification = false |
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12 | SET foundationsym = false |
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13 | SET implementationfiletype = Ngc |
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14 | SET package = csg324 |
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15 | SET removerpms = false |
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16 | SET simulationfiles = Behavioral |
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17 | SET speedgrade = -3 |
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18 | SET verilogsim = false |
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19 | SET vhdlsim = true |
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20 | SET workingdirectory = .\tmp\ |
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21 | |
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22 | # CRC: 1242dfe7 |
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