source: PROJECT_CORE_MPI/MPI_HCL/TRUNK/Test_Timer/ipcore_dir/mem_coregen.cgp @ 119

# Date: Sun Mar 02 19:33:45 2014

SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = .\tmp\

# CRC: 1242dfe7