[115] | 1 | SET_FLAG DEBUG FALSE |
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| 2 | SET_FLAG MODE INTERACTIVE |
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| 3 | SET_FLAG STANDALONE_MODE FALSE |
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| 4 | SET_PREFERENCE devicefamily spartan6 |
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| 5 | SET_PREFERENCE device xc6slx45 |
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| 6 | SET_PREFERENCE speedgrade -3 |
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| 7 | SET_PREFERENCE package csg324 |
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| 8 | SET_PREFERENCE verilogsim false |
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| 9 | SET_PREFERENCE vhdlsim true |
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| 10 | SET_PREFERENCE simulationfiles Behavioral |
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| 11 | SET_PREFERENCE busformat BusFormatAngleBracketNotRipped |
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| 12 | SET_PREFERENCE outputdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/ |
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| 13 | SET_PREFERENCE workingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/ |
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| 14 | SET_PREFERENCE subworkingdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/ |
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| 15 | SET_PREFERENCE transientdirectory D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/_dbg/ |
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| 16 | SET_PREFERENCE designentry VHDL |
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| 17 | SET_PREFERENCE flowvendor Other |
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| 18 | SET_PREFERENCE addpads false |
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| 19 | SET_PREFERENCE projectname coregen |
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| 20 | SET_PREFERENCE formalverification false |
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| 21 | SET_PREFERENCE asysymbol false |
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| 22 | SET_PREFERENCE implementationfiletype Ngc |
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| 23 | SET_PREFERENCE foundationsym false |
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| 24 | SET_PREFERENCE createndf false |
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| 25 | SET_PREFERENCE removerpms false |
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| 26 | SET_PARAMETER Component_Name mem_4k8 |
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| 27 | SET_PARAMETER Interface_Type Native |
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| 28 | SET_PARAMETER AXI_Type AXI4_Full |
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| 29 | SET_PARAMETER AXI_Slave_Type Memory_Slave |
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| 30 | SET_PARAMETER Use_AXI_ID false |
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| 31 | SET_PARAMETER AXI_ID_Width 4 |
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| 32 | SET_PARAMETER Memory_Type Simple_Dual_Port_RAM |
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| 33 | SET_PARAMETER ecctype No_ECC |
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| 34 | SET_PARAMETER ECC false |
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| 35 | SET_PARAMETER softecc false |
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| 36 | SET_PARAMETER Use_Error_Injection_Pins false |
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| 37 | SET_PARAMETER Error_Injection_Type Single_Bit_Error_Injection |
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| 38 | SET_PARAMETER Use_Byte_Write_Enable true |
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| 39 | SET_PARAMETER Byte_Size 8 |
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| 40 | SET_PARAMETER Algorithm Minimum_Area |
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| 41 | SET_PARAMETER Primitive 8kx2 |
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| 42 | SET_PARAMETER Assume_Synchronous_Clk false |
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| 43 | SET_PARAMETER Write_Width_A 8 |
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| 44 | SET_PARAMETER Write_Depth_A 4096 |
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| 45 | SET_PARAMETER Read_Width_A 8 |
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| 46 | SET_PARAMETER Operating_Mode_A WRITE_FIRST |
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| 47 | SET_PARAMETER Enable_A Use_ENA_Pin |
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| 48 | SET_PARAMETER Write_Width_B 8 |
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| 49 | SET_PARAMETER Read_Width_B 8 |
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| 50 | SET_PARAMETER Operating_Mode_B WRITE_FIRST |
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| 51 | SET_PARAMETER Enable_B Use_ENB_Pin |
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| 52 | SET_PARAMETER Register_PortA_Output_of_Memory_Primitives false |
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| 53 | SET_PARAMETER Register_PortA_Output_of_Memory_Core false |
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| 54 | SET_PARAMETER Use_REGCEA_Pin false |
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| 55 | SET_PARAMETER Register_PortB_Output_of_Memory_Primitives false |
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| 56 | SET_PARAMETER Register_PortB_Output_of_Memory_Core false |
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| 57 | SET_PARAMETER Use_REGCEB_Pin false |
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| 58 | SET_PARAMETER register_porta_input_of_softecc false |
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| 59 | SET_PARAMETER register_portb_output_of_softecc false |
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| 60 | SET_PARAMETER Pipeline_Stages 0 |
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| 61 | SET_PARAMETER Load_Init_File false |
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| 62 | SET_PARAMETER Coe_File no_coe_file_loaded |
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| 63 | SET_PARAMETER Fill_Remaining_Memory_Locations false |
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| 64 | SET_PARAMETER Remaining_Memory_Locations 0 |
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| 65 | SET_PARAMETER Use_RSTA_Pin false |
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| 66 | SET_PARAMETER Reset_Memory_Latch_A false |
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| 67 | SET_PARAMETER Reset_Priority_A CE |
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| 68 | SET_PARAMETER Output_Reset_Value_A 0 |
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| 69 | SET_PARAMETER Use_RSTB_Pin false |
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| 70 | SET_PARAMETER Reset_Memory_Latch_B false |
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| 71 | SET_PARAMETER Reset_Priority_B CE |
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| 72 | SET_PARAMETER Output_Reset_Value_B 0 |
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| 73 | SET_PARAMETER Reset_Type SYNC |
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| 74 | SET_PARAMETER Additional_Inputs_for_Power_Estimation false |
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| 75 | SET_PARAMETER Port_A_Clock 100 |
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| 76 | SET_PARAMETER Port_A_Write_Rate 50 |
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| 77 | SET_PARAMETER Port_B_Clock 100 |
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| 78 | SET_PARAMETER Port_B_Write_Rate 0 |
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| 79 | SET_PARAMETER Port_A_Enable_Rate 100 |
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| 80 | SET_PARAMETER Port_B_Enable_Rate 100 |
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| 81 | SET_PARAMETER Collision_Warnings ALL |
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| 82 | SET_PARAMETER Disable_Collision_Warnings false |
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| 83 | SET_PARAMETER Disable_Out_of_Range_Warnings false |
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| 84 | SET_CORE_NAME Block Memory Generator |
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| 85 | SET_CORE_VERSION 6.2 |
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| 86 | SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2 |
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| 87 | SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2 |
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| 88 | SET_CORE_PATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2 |
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| 89 | SET_CORE_GUIPATH C:/Xilinx/13.3/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tcl |
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| 90 | SET_CORE_DATASHEET C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf |
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| 91 | ADD_CORE_DOCUMENT <C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf><blk_mem_gen_ds512.pdf> |
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| 92 | ADD_CORE_DOCUMENT <C:\Xilinx\13.3\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_v6_2_vinfo.html><blk_mem_gen_v6_2_vinfo.html> |
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