Last change
on this file since 127 was
115,
checked in by rolagamo, 11 years ago
|
Ajout des Cores utilisés dans le projet
|
File size:
772 bytes
|
Rev | Line | |
---|
[115] | 1 | <?xml version="1.0" encoding="UTF-8"?> |
---|
| 2 | <!-- IMPORTANT: This is an internal file that has been generated --> |
---|
| 3 | <!-- by the Xilinx ISE software. Any direct editing or --> |
---|
| 4 | <!-- changes made to this file may result in unpredictable --> |
---|
| 5 | <!-- behavior or data corruption. It is strongly advised that --> |
---|
| 6 | <!-- users do not edit the contents of this file. --> |
---|
| 7 | <!-- --> |
---|
| 8 | <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> |
---|
| 9 | |
---|
| 10 | <messages> |
---|
| 11 | <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "D:/MPI_HCL/Test_Timer/ipcore_dir/tmp/_cg/blk_mem_gen_v6_2.vhd" into library work</arg> |
---|
| 12 | </msg> |
---|
| 13 | |
---|
| 14 | </messages> |
---|
| 15 | |
---|
Note: See
TracBrowser
for help on using the repository browser.