[96] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU |
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| 4 | -- |
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| 5 | -- Create Date: 04:57:14 07/15/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: load_instr - Behavioral |
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| 8 | -- Project Name: MPI CORE |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Ce module permet de charger une instruction dans le FIFO 1 |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | library NocLib; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | use IEEE.NUMERIC_STD.ALL; |
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| 27 | use NocLib.CoreTypes.all; |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity load_instr is |
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| 34 | Port ( Instruction : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 35 | Instruction_en : in STD_LOGIC; |
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| 36 | |
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| 37 | clk : in STD_LOGIC; |
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| 38 | reset : in STD_LOGIC; |
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| 39 | dma_rd_grant : in STD_LOGIC; |
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| 40 | dma_rd_request : out STD_LOGIC:='0'; |
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| 41 | instruction_ack : out STD_LOGIC:='0'; |
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| 42 | fifo_din : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 43 | fifo_wr :out std_logic:='0'; |
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| 44 | copying :out std_logic:='0'; |
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| 45 | fifo_full : in STD_LOGIC; |
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| 46 | ram_address_rd : buffer STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 47 | ram_data : in STD_LOGIC_VECTOR (WORD-1 downto 0); |
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| 48 | Ram_rd_en : out std_logic); |
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| 49 | end load_instr; |
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| 50 | |
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| 51 | architecture Behavioral of load_instr is |
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| 52 | --déclaration des types manipulés |
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| 53 | type typ_loadinst is (init,setadr,readptr,getbus,readmem,freebus,st_timeout); |
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| 54 | --déclaration des signaux |
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| 55 | signal Ram_address_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); |
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| 56 | --signal ptr, ptr_i:STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); --pointeur vers l'instruction en RAM |
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| 57 | signal Base_Adr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0):=(others=>'0'); |
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| 58 | signal adr_ptr : natural range 0 to 65536:=0; |
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| 59 | signal Base_AdrSet : std_logic:='0' ; --indique l'adresse de base des instructions positionée |
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| 60 | signal fifo_din_i:std_logic_vector(WORD-1 downto 0):=(others=>'-'); |
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| 61 | signal iLen,iLen_i : natural range 0 to 15:=0; --longueur de l'instruction à copier dans le Fifo |
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| 62 | signal fifo_wr_i :std_logic:='0'; |
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| 63 | signal base_adrset_i : std_logic:='0'; |
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| 64 | signal instruction_ack_i :std_logic:='0'; |
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| 65 | signal Dma_rd_request_i :std_logic:='0'; |
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| 66 | signal count,count_i : natural range 0 to 31:=0; --permet de faie évoluer la sous-MAE |
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| 67 | signal etloadinst,next_loadinst : typ_loadinst; |
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| 68 | begin |
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| 69 | SYNC_PROC: process (clk) |
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| 70 | begin |
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| 71 | if rising_edge(clk) then |
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| 72 | if (reset = '1') or instruction_en='0' then |
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| 73 | etloadinst <= init; |
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| 74 | Base_adrSet<= '0'; |
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| 75 | dma_rd_request<='0'; |
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| 76 | instruction_ack<='0'; |
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| 77 | else |
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| 78 | etloadinst <= next_loadinst; |
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| 79 | fifo_din <= fifo_din_i; |
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| 80 | Base_AdrSet<=Base_adrSet_i; |
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| 81 | ram_address_rd<=ram_address_i; |
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| 82 | adr_ptr<=to_integer(unsigned(ram_address_i)); |
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| 83 | dma_rd_request<=dma_rd_request_i; |
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| 84 | instruction_ack<=instruction_ack_i; |
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| 85 | count<=count_i; |
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| 86 | Ilen<=Ilen_i; |
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| 87 | |
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| 88 | |
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| 89 | -- assign other outputs to internal signals |
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| 90 | end if; |
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| 91 | end if; |
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| 92 | end process; |
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| 93 | |
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| 94 | -- |
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| 95 | OUTPUT_DECODE: process (etloadinst,Count_i,Ram_data,Dma_rd_grant,fifo_wr_i) |
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| 96 | variable Adr_inst1,adr_inst2 : natural; |
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| 97 | begin |
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| 98 | --insert statements to decode internal output signals |
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| 99 | --below is simple example |
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| 100 | case etloadinst is |
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| 101 | when init => |
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| 102 | Dma_rd_request_i<='0'; |
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| 103 | fifo_wr<='0'; |
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| 104 | copying<='0'; |
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| 105 | Ram_rd_en<='0'; |
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| 106 | Instruction_ack_i<='0'; |
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| 107 | fifo_din_i<=(others=>'-'); |
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| 108 | Base_AdrSet_i<='0'; |
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| 109 | |
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| 110 | when SetAdr => |
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| 111 | Dma_rd_request_i<='0'; |
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| 112 | Instruction_ack_i<='0'; |
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| 113 | fifo_wr<='0'; |
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| 114 | copying<='0'; |
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| 115 | Ram_rd_en<='0'; |
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| 116 | |
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| 117 | fifo_din_i<=(others=>'-'); |
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| 118 | Base_AdrSet_i<='1'; |
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| 119 | |
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| 120 | when getbus => |
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| 121 | fifo_wr<='0'; |
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| 122 | copying<='1'; |
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| 123 | Ram_rd_en<=Dma_rd_grant; |
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| 124 | Dma_rd_request_i<='1'; |
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| 125 | Instruction_ack_i<='0'; |
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| 126 | fifo_din_i<=(others=>'-'); |
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| 127 | Base_AdrSet_i<='1'; |
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| 128 | when readptr => |
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| 129 | fifo_wr<='0'; |
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| 130 | |
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| 131 | copying<='1'; |
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| 132 | Ram_rd_en<='1'; |
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| 133 | Dma_rd_request_i<='1'; |
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| 134 | Instruction_ack_i<='0'; |
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| 135 | fifo_din_i<=(others=>'-'); |
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| 136 | Base_AdrSet_i<='1'; |
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| 137 | when readmem => |
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| 138 | Dma_rd_request_i<='1'; |
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| 139 | copying<='1'; |
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| 140 | Ram_rd_en<='1'; |
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| 141 | fifo_wr<=fifo_wr_i; |
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| 142 | fifo_din_i<=Ram_data; |
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| 143 | Base_AdrSet_i<='1'; |
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| 144 | Instruction_ack_i<='0'; |
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| 145 | |
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| 146 | when freebus => |
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| 147 | Dma_rd_request_i<='0'; |
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| 148 | fifo_wr<='0'; |
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| 149 | copying<='0'; |
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| 150 | Ram_rd_en<='0'; |
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| 151 | Instruction_ack_i<='1'; |
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| 152 | fifo_din_i<=(others=>'-'); |
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| 153 | Base_AdrSet_i<='1'; |
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| 154 | when st_timeout => |
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| 155 | Dma_rd_request_i<='0'; |
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| 156 | fifo_wr<='0'; |
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| 157 | copying<='0'; |
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| 158 | Ram_rd_en<='0'; |
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| 159 | Instruction_ack_i<='0'; |
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| 160 | fifo_din_i<=(others=>'-'); |
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| 161 | Base_AdrSet_i<='1'; |
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| 162 | end case; |
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| 163 | end process; |
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| 164 | |
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| 165 | NEXT_STATE_DECODE: process (etloadinst, Ram_address_rd,Base_AdrSet,Ram_data,Instruction,instruction_en, fifo_full,dma_rd_grant,count,Ilen) |
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| 166 | |
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| 167 | variable ptr : std_logic_vector(ADRLEN-1 downto 0); |
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| 168 | variable timeout: natural range 0 to 255; |
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| 169 | variable Base_AD,ADRtmp,iptr : natural range 0 to 65535; |
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| 170 | begin |
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| 171 | --declare default state for next_state to avoid latches |
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| 172 | next_loadinst <= etloadinst; --default is to stay in current state |
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| 173 | Ram_address_i<=Ram_address_rd; |
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| 174 | --below is a simple example |
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| 175 | case (etloadinst) is |
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| 176 | when init => if base_adrset='1' and Instruction_en='1' then |
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| 177 | Ilen_i<=to_integer(unsigned(Instruction(3 downto 0)));--initialisation de longueur |
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| 178 | next_loadinst<=getbus; |
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| 179 | elsif Instruction_en='1' then |
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| 180 | next_loadinst<=Setadr; |
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| 181 | Base_Adr<=X"0000"; |
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| 182 | else |
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| 183 | next_loadinst<=init; |
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| 184 | Base_Adr<=X"0000"; |
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| 185 | Ilen_i<=0; |
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| 186 | end if; |
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| 187 | fifo_wr_i<='0'; |
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| 188 | count_i<=0; |
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| 189 | |
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| 190 | -- |
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| 191 | When Setadr => if Base_adrSet='0' then |
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| 192 | Base_Adr<=std_logic_vector(to_unsigned(Core_upper_adr,8)) & X"00"; --récupération des bits de poids forts de l'instruction |
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| 193 | -- |
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| 194 | end if; |
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| 195 | next_loadinst<=init; |
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| 196 | Ram_address_i<=(others=>'0'); |
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| 197 | count_i<=0; |
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| 198 | when getbus => |
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| 199 | BASE_AD:=to_integer(unsigned(base_adr)); |
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| 200 | if dma_rd_grant = '1' then |
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| 201 | next_loadinst <= readptr; |
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| 202 | |
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| 203 | -- prépare la prochaine lecture |
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| 204 | |
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| 205 | else |
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| 206 | |
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| 207 | end if; |
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| 208 | Ram_address_i<=(others=>'0'); |
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| 209 | count_i<=0; |
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| 210 | When readptr => |
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| 211 | --s'assurer que le bus est disponible |
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| 212 | |
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| 213 | if count=0 then |
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| 214 | |
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| 215 | Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+2,16)); |
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| 216 | if dma_rd_grant='1' then |
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| 217 | count_i <=count+1; |
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| 218 | end if; |
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| 219 | elsif count=1 then-- attend que la donnée soit positionnée |
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| 220 | if dma_rd_grant = '1' then |
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| 221 | count_i <=count+1; |
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| 222 | end if; |
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| 223 | elsif count=2 then |
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| 224 | if dma_rd_grant = '1' then |
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| 225 | count_i <=count+1; |
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| 226 | ptr(Word-1 downto 0):=Ram_data; |
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| 227 | else |
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| 228 | count_i<=0; |
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| 229 | end if; |
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| 230 | Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); |
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| 231 | |
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| 232 | elsif count=3 then |
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| 233 | Ram_address_i<=std_logic_vector(to_unsigned(BASE_AD+3,16)); |
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| 234 | if dma_rd_grant = '1' then |
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| 235 | count_i <=count+1; |
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| 236 | end if; |
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| 237 | elsif count=4 then |
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| 238 | if dma_rd_grant = '1' then |
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| 239 | ptr(15 downto 8):=Ram_data; |
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| 240 | count_i<=0; |
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| 241 | timeout:=0; |
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| 242 | next_loadinst <= readmem; |
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| 243 | else |
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| 244 | count_i<=3; |
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| 245 | end if; |
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| 246 | report "Readptr " & image(ptr); |
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| 247 | else |
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| 248 | |
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| 249 | end if; |
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| 250 | |
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| 251 | if dma_rd_grant = '0' then |
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| 252 | assert true report "Mauvaise lecture" severity failure; |
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| 253 | timeout:=timeout+1; |
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| 254 | end if; |
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| 255 | when readmem => |
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| 256 | if fifo_full='0' then |
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| 257 | if ilen >0 then |
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| 258 | if count=0 then |
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| 259 | iptr:=to_integer(unsigned(ptr)); |
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| 260 | AdrTmp:=iptr; |
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| 261 | if dma_rd_grant = '1' then |
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| 262 | count_i <=count+1; |
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| 263 | fifo_wr_i<='0'; |
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| 264 | end if; |
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| 265 | elsif count=1 then |
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| 266 | if dma_rd_grant = '1' then |
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| 267 | count_i <=count+1; |
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| 268 | fifo_wr_i<='0'; |
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| 269 | end if; |
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| 270 | elsif count=2 then |
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| 271 | if dma_rd_grant = '1' then |
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| 272 | count_i <=count+1; |
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| 273 | fifo_wr_i<='0'; |
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| 274 | else |
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| 275 | count_i<=1; |
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| 276 | end if; |
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| 277 | elsif count=3 then |
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| 278 | count_i <=count+1; |
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| 279 | fifo_wr_i<='1'; --écriture de la donnée dans le fifo |
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| 280 | Ilen_i<=Ilen-1; |
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| 281 | AdrTmp:=Adr_Ptr+1; |
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| 282 | elsif count=4 then |
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| 283 | fifo_wr_i<='0'; |
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| 284 | count_i<=1; |
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| 285 | end if; |
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| 286 | else --Ilen=0 ? |
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| 287 | fifo_wr_i<='0'; |
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| 288 | next_loadinst<=freebus; |
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| 289 | end if; |
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| 290 | end if; |
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| 291 | |
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| 292 | Ram_address_i<=STD_LOGIC_VECTOR(to_unsigned(AdrTmp,16)); |
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| 293 | if dma_rd_grant = '0' or Fifo_full='1' then |
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| 294 | timeout:=timeout+1; |
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| 295 | fifo_wr_i<='0'; |
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| 296 | Count_i<=1; --recommencer les cycles d'attente de la donnée |
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| 297 | if timeout=200 then |
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| 298 | next_loadinst<=st_timeout; |
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| 299 | end if; |
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| 300 | end if; |
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| 301 | |
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| 302 | when freebus => |
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| 303 | fifo_wr_i<='0'; |
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| 304 | count_i<=0; |
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| 305 | Ram_address_i<=(others=>'0'); |
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| 306 | if instruction_en='0' then |
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| 307 | next_loadinst <= init; |
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| 308 | end if; |
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| 309 | when st_timeout => |
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| 310 | fifo_wr_i<='0'; |
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| 311 | Ram_address_i<=(others=>'0'); |
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| 312 | next_loadinst<=init; |
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| 313 | report "Copie D'instruction *** RAM/Fifo a été indisponible pour trop longtemps !!!"; |
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| 314 | count_i<=0; |
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| 315 | end case; |
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| 316 | end process; |
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| 317 | |
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| 318 | end Behavioral; |
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| 319 | |
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