[24] | 1 | -- Package File Template |
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| 2 | -- |
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| 3 | -- Purpose: This package defines supplemental types, subtypes, |
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| 4 | -- constants, and components |
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| 5 | |
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| 6 | |
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| 7 | library IEEE; |
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| 8 | use IEEE.STD_LOGIC_1164.all; |
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| 9 | |
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| 10 | package CoreTypes is |
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| 11 | CONSTANT Word :POSITIVE:= 8; |
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| 12 | CONSTANT ADRLEN:POSITIVE:=16; |
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| 13 | CONSTANT LZFILL :std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');--indique le nombre de zero à utiliser pour completer le bus de données lorsque la longueur restante du bus d'adresse est inférueure à la largeur du bus de données |
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| 14 | CONSTANT IADR0 : NATURAL :=2; --Adresse basse de l'instruction |
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| 15 | CONSTANT IADR1 : natural :=3; |
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| 16 | CONSTANT CORE_BASE_ADR :natural range 0 to 65535:=4096; |
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| 17 | CONSTANT CORE_UPPER_ADR : natural range 0 to 255:=16; |
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| 18 | CONSTANT CORE_GET_ADR:natural:=CORE_BASE_ADR+526; |
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| 19 | CONSTANT CORE_PUT_ADR :natural:=CORE_BASE_ADR+516; |
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| 20 | CONSTANT core_INIT_ADR : natural:=CORE_BASE_ADR+512; |
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| 21 | CONSTANT CORE_WCREATE_ADR : natural := CORE_BASE_ADR+536; |
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| 22 | CONSTANT CORE_WCOMPL_ADR : natural := CORE_BASE_ADR+546; |
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| 23 | CONSTANT CORE_WPOST_ADR : natural := CORE_BASE_ADR+556; |
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| 24 | CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566; |
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| 25 | CONSTANT CORE_Rank2port_BASE :NATURAL:=32; |
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| 26 | CONSTANT WIN0_ADR :natural :=4; |
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| 27 | CONSTANT WIN1_ADR :natural :=14; |
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| 28 | CONSTANT WIN2_ADR :natural :=24; |
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| 29 | CONSTANT WIN3_ADR :natural :=34; |
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| 30 | CONSTANT GETPORTID : std_logic_vector(3 downto 0):="0001"; |
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| 31 | |
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| 32 | type Typ_PortIO is |
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| 33 | array(natural range <>) of std_logic_vector( Word-1 downto 0); |
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| 34 | |
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| 35 | type memory is |
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| 36 | array (natural range <>) of std_logic_vector(word-1 downto 0); |
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| 37 | |
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| 38 | type Core_io is |
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| 39 | record |
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| 40 | Instr_en :std_logic; -- active une instruction MPI |
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| 41 | Instr_ack :std_logic;-- signal la prise en compte de l'instruction |
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| 42 | Ready :std_logic;-- indique que la dernière fonction est terminée |
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| 43 | InitOk :std_logic; -- l'initialisation est terminée |
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| 44 | Hold_Req :std_logic;--Demande DMA |
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| 45 | Hold_Ack :std_logic;-- Autorisation DMA |
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| 46 | MemBusy :std_logic;-- active le refus de DMA (1 -> ignoré la requête DMA) |
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| 47 | RamSel :std_logic;-- indique le statut de la RAM (0 ->dispo 1->occupé par Core_MPI) |
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| 48 | IntState1 : natural range 0 to 255; --permet de stocker l'état des MAE interne dans les procédures |
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| 49 | IntState2 : natural range 0 to 255; |
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| 50 | Instruction :std_logic_vector (word-1 downto 0); |
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| 51 | WinId :natural range 0 to 255; --stocke le dernier Id utilisé par WinCreate |
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| 52 | IsMain : std_logic; -- indique si la librairie est principal |
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| 53 | Rank : natural range 0 to 16; --donne le rang du processus courant |
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| 54 | end record; |
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| 55 | |
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| 56 | type typ_dpram is |
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| 57 | record |
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| 58 | |
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| 59 | |
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| 60 | clk_wr : STD_LOGIC; |
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| 61 | clk_rd : STD_LOGIC; |
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| 62 | we : STD_LOGIC; |
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| 63 | ena : STD_LOGIC; |
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| 64 | enb : STD_LOGIC; |
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| 65 | addr_wr: STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 66 | addr_rd : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 67 | data_in : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 68 | data_out : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 69 | |
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| 70 | |
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| 71 | end record; |
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| 72 | type Typ_MPIPort_in is |
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| 73 | record |
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| 74 | instruction : STD_LOGIC_VECTOR (Word -1 downto 0); |
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| 75 | instruction_en : STD_LOGIC; |
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| 76 | |
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| 77 | |
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| 78 | packet_ack : std_logic; |
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| 79 | ram_data_out : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 80 | |
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| 81 | hold_ack : STD_Logic; --autorisation par l'application |
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| 82 | clk : STD_LOGIC; |
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| 83 | reset : STD_LOGIC; |
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| 84 | |
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| 85 | end record; |
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| 86 | type Typ_MPIPort_out is |
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| 87 | record |
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| 88 | |
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| 89 | |
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| 90 | ram_we : STD_LOGIC; |
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| 91 | ram_en : STD_LOGIC; |
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| 92 | ram_data_in : STD_LOGIC_VECTOR (WORD-1 downto 0); |
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| 93 | ram_address_rd : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 94 | ram_address_wr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 95 | packet_received : STD_LOGIC; |
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| 96 | barrier_completed : STD_LOGIC; |
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| 97 | instruction_fifo_full : STD_LOGIC; |
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| 98 | PushOut : STD_LOGIC_VECTOR (WORD-1 downto 0); |
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| 99 | |
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| 100 | hold_req : STD_Logic; --requete vers application |
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| 101 | end record; |
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| 102 | |
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| 103 | Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in; |
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| 104 | Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out; |
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| 105 | |
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| 106 | -- Declare constants |
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| 107 | |
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| 108 | -- constant <constant_name> : time := <time_unit> ns; |
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| 109 | -- constant <constant_name> : integer := <value>; |
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| 110 | -- |
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| 111 | -- Declare functions and procedure |
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| 112 | Component SWITCH_GEN is |
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| 113 | generic(number_of_ports : positive := 8); |
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| 114 | port( |
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| 115 | -- ports d'entree |
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| 116 | Port_in : in typ_portIO(1 to number_of_ports) ; |
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| 117 | -- |
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| 118 | |
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| 119 | -- port de sortie |
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| 120 | Port_out : out typ_portIO(1 to number_of_ports); |
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| 121 | -- |
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| 122 | -- signaux de controle |
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| 123 | cmd_in_en : in std_logic_vector(number_of_ports downto 1); |
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| 124 | data_in_en : in std_logic_vector(number_of_ports downto 1); |
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| 125 | data_out_en : in std_logic_vector(number_of_ports downto 1); |
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| 126 | fifo_in_full : out std_logic_vector(number_of_ports downto 1); |
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| 127 | fifo_in_empty : out std_logic_vector(number_of_ports downto 1); |
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| 128 | data_available : out std_logic_vector(number_of_ports downto 1); |
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| 129 | clk : in STD_LOGIC; |
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| 130 | reset : in STD_LOGIC); |
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| 131 | end component SWITCH_GEN; |
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| 132 | -- déclaration des fonctions utilisées |
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| 133 | |
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| 134 | FUNCTION all_ones(s1:std_logic_vector) return std_logic; |
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| 135 | --This function returns if the input vector has all ones and no zeros |
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| 136 | FUNCTION all_zeros(s1:std_logic_vector) return std_logic; |
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| 137 | --This function returns if the input vector has all zeros and no ones |
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| 138 | FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; |
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| 139 | --This function increments an std_logic_vector type by '1', without |
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| 140 | --using any arithmatic |
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| 141 | |
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| 142 | FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; |
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| 143 | --This function decrements an std_logic_vector type by '1', without |
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| 144 | --using any arithmatic |
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| 145 | FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector; |
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| 146 | --renvoie un std_logic_vector de taille ADRLEN |
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| 147 | Function Stdlv (s1 : natural ) return std_logic_vector; |
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| 148 | end CoreTypes; |
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| 149 | |
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| 150 | |
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| 151 | Package body CoreTypes is |
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| 152 | |
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| 153 | |
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| 154 | FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is |
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| 155 | --this function increments a std_logic_vector type by '1' |
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| 156 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 157 | VARIABLE tb : std_logic_vector(s1'high downto s1'low); |
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| 158 | BEGIN |
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| 159 | tb(s1'low) := en; |
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| 160 | V := s1; |
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| 161 | for i in (V'low + 1) to V'high loop |
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| 162 | tb(i) := V(i - 1) and tb(i -1); |
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| 163 | end loop; |
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| 164 | for i in V'low to V'high loop |
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| 165 | if(tb(i) = '1') then |
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| 166 | V(i) := not(V(i)); |
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| 167 | end if; |
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| 168 | end loop; |
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| 169 | return V; |
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| 170 | end incr_vec; -- end function |
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| 171 | |
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| 172 | FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is |
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| 173 | --this function decrements a std_logic_vector type by '1' |
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| 174 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 175 | VARIABLE tb : std_logic_vector(s1'high downto s1'low); |
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| 176 | BEGIN |
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| 177 | tb(s1'low) := not(en); |
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| 178 | V := s1; |
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| 179 | for i in (V'low + 1) to V'high loop |
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| 180 | tb(i) := V(i - 1) or tb(i -1); |
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| 181 | end loop; |
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| 182 | for i in V'low to V'high loop |
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| 183 | if(tb(i) = '0') then |
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| 184 | V(i) := not(V(i)); |
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| 185 | end if; |
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| 186 | end loop; |
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| 187 | return V; |
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| 188 | end dcr_vec; -- end function |
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| 189 | FUNCTION all_ones(s1:std_logic_vector) return std_logic is |
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| 190 | --this function tells if all bits of a vector are '1' |
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| 191 | --return value Z is '1', then vector has all 1 bits |
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| 192 | --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 193 | VARIABLE Z : std_logic; |
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| 194 | BEGIN |
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| 195 | Z := s1(s1'low); |
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| 196 | FOR i IN (s1'low+1) to s1'high LOOP |
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| 197 | Z := Z AND s1(i); |
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| 198 | END LOOP; |
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| 199 | RETURN Z; |
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| 200 | END all_ones; -- end function |
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| 201 | FUNCTION all_zeros(s1:std_logic_vector) return std_logic is |
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| 202 | --this function tells if all bits of a vector are '0' |
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| 203 | --return value Z if '1', then vector has all 0 bits |
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| 204 | --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 205 | VARIABLE Z : std_logic; |
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| 206 | BEGIN |
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| 207 | Z := '0'; |
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| 208 | FOR i IN (s1'low) to s1'high LOOP |
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| 209 | Z := Z OR s1(i); |
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| 210 | END LOOP; |
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| 211 | RETURN not(Z); |
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| 212 | END all_zeros; -- end function |
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| 213 | |
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| 214 | FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector is |
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| 215 | --cette fonction fait roter un STD_logic d'un pas vers la gauche |
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| 216 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 217 | VARIABLE lb : std_logic :=s1(s1'left); |
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| 218 | BEGIN |
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| 219 | |
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| 220 | for i in V'left downto (V'right+1) loop |
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| 221 | V(i) := s1(i - 1) ; |
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| 222 | end loop; |
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| 223 | V(V'right):=lb; |
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| 224 | return V; |
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| 225 | end Rol_vec; |
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| 226 | Function Stdlv (s1 : natural ) return std_logic_vector is |
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| 227 | VARIABLE V : std_logic_vector(ADRLEN-1 downto 0) |
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| 228 | begin |
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| 229 | V:=std_logic_vector(to_unsigned(s1,ADRLEN)); |
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| 230 | return V; |
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| 231 | end stdlv; |
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| 232 | end CoreTypes; |
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