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INPUT_PORT_MODULE.syr @ 24

Last change on this file since 24 was 24, checked in by rolagamo, 12 years ago

File size: 25.9 KB

Line
1	Release 11.1 - xst L.33 (nt)
2	Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.
3	--> Parameter TMPDIR set to xst/projnav.tmp
4
5
6	Total REAL time to Xst completion: 0.00 secs
7	Total CPU time to Xst completion: 0.18 secs
8
9	--> Parameter xsthdpdir set to xst
10
11
12	Total REAL time to Xst completion: 0.00 secs
13	Total CPU time to Xst completion: 0.18 secs
14
15	--> Reading design: INPUT_PORT_MODULE.prj
16
17	TABLE OF CONTENTS
18	1) Synthesis Options Summary
19	2) HDL Compilation
20	3) Design Hierarchy Analysis
21	4) HDL Analysis
22	5) HDL Synthesis
23	5.1) HDL Synthesis Report
24	6) Advanced HDL Synthesis
25	6.1) Advanced HDL Synthesis Report
26	7) Low Level Synthesis
27	8) Partition Report
28	9) Final Report
29	9.1) Device utilization summary
30	9.2) Partition Resource Summary
31	9.3) TIMING REPORT
32
33
34	=========================================================================
35	* Synthesis Options Summary *
36	=========================================================================
37	---- Source Parameters
38	Input File Name : "INPUT_PORT_MODULE.prj"
39	Input Format : mixed
40	Ignore Synthesis Constraint File : NO
41
42	---- Target Parameters
43	Output File Name : "INPUT_PORT_MODULE"
44	Output Format : NGC
45	Target Device : xc3s1200e-4-fg320
46
47	---- Source Options
48	Top Module Name : INPUT_PORT_MODULE
49	Automatic FSM Extraction : YES
50	FSM Encoding Algorithm : Auto
51	Safe Implementation : No
52	FSM Style : lut
53	RAM Extraction : Yes
54	RAM Style : Auto
55	ROM Extraction : Yes
56	Mux Style : Auto
57	Decoder Extraction : YES
58	Priority Encoder Extraction : YES
59	Shift Register Extraction : YES
60	Logical Shifter Extraction : YES
61	XOR Collapsing : YES
62	ROM Style : Auto
63	Mux Extraction : YES
64	Resource Sharing : YES
65	Asynchronous To Synchronous : NO
66	Automatic Register Balancing : No
67
68	---- Target Options
69	Add IO Buffers : YES
70	Add Generic Clock Buffer(BUFG) : 24
71	Register Duplication : YES
72	Slice Packing : YES
73	Optimize Instantiated Primitives : NO
74	Use Clock Enable : Yes
75	Use Synchronous Set : Yes
76	Use Synchronous Reset : Yes
77	Pack IO Registers into IOBs : auto
78	Equivalent register Removal : YES
79
80	---- General Options
81	Optimization Goal : Speed
82	Optimization Effort : 1
83	Library Search Order : INPUT_PORT_MODULE.lso
84	Keep Hierarchy : NO
85	Netlist Hierarchy : as_optimized
86	RTL Output : Yes
87	Global Optimization : AllClockNets
88	Read Cores : YES
89	Write Timing Constraints : NO
90	Cross Clock Analysis : NO
91	Hierarchy Separator : /
92	Bus Delimiter : <>
93	Case Specifier : maintain
94	Slice Utilization Ratio : 100
95	BRAM Utilization Ratio : 100
96	Verilog 2001 : YES
97	Auto BRAM Packing : NO
98	Slice Utilization Ratio Delta : 5
99
100	=========================================================================
101
102
103	=========================================================================
104	* HDL Compilation *
105	=========================================================================
106	Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd" in Library work.
107	Architecture behavioral of Entity ram_256 is up to date.
108	Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd" in Library work.
109	Architecture behavioral of Entity fifo_256_fwft is up to date.
110	Compiling vhdl file "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd" in Library work.
111	Entity <input_port_module> compiled.
112	Entity <input_port_module> (Architecture <behavioral>) compiled.
113
114	=========================================================================
115	* Design Hierarchy Analysis *
116	=========================================================================
117	Analyzing hierarchy for entity <INPUT_PORT_MODULE> in library <work> (architecture <behavioral>) with generics.
118	number_of_ports = 4
119
120	Analyzing hierarchy for entity <FIFO_256_FWFT> in library <work> (architecture <behavioral>).
121
122	Analyzing hierarchy for entity <RAM_256> in library <work> (architecture <behavioral>).
123
124
125	=========================================================================
126	* HDL Analysis *
127	=========================================================================
128	Analyzing generic Entity <INPUT_PORT_MODULE> in library <work> (Architecture <behavioral>).
129	number_of_ports = 4
130	Entity <INPUT_PORT_MODULE> analyzed. Unit <INPUT_PORT_MODULE> generated.
131
132	Analyzing Entity <FIFO_256_FWFT> in library <work> (Architecture <behavioral>).
133	Entity <FIFO_256_FWFT> analyzed. Unit <FIFO_256_FWFT> generated.
134
135	Analyzing Entity <RAM_256> in library <work> (Architecture <behavioral>).
136	Entity <RAM_256> analyzed. Unit <RAM_256> generated.
137
138
139	=========================================================================
140	* HDL Synthesis *
141	=========================================================================
142
143	Performing bidirectional port resolution...
144
145	Synthesizing Unit <RAM_256>.
146	Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/RAM_256.vhd".
147	Found 256x8-bit dual-port RAM <Mram_RAM> for signal <RAM>.
148	Found 8-bit register for signal <dob>.
149	Summary:
150	inferred 1 RAM(s).
151	inferred 8 D-type flip-flop(s).
152	Unit <RAM_256> synthesized.
153
154
155	Synthesizing Unit <FIFO_256_FWFT>.
156	Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/FIFO_256_FWFT.vhd".
157	Found finite state machine <FSM_0> for signal <fwft_fsm_state>.
158	-----------------------------------------------------------------------
159	\| States \| 3 \|
160	\| Transitions \| 8 \|
161	\| Inputs \| 3 \|
162	\| Outputs \| 4 \|
163	\| Clock \| clk (rising_edge) \|
164	\| Reset \| srst (positive) \|
165	\| Reset type \| synchronous \|
166	\| Reset State \| state0 \|
167	\| Power Up State \| state0 \|
168	\| Encoding \| automatic \|
169	\| Implementation \| LUT \|
170	-----------------------------------------------------------------------
171	Found 8-bit register for signal <doa_signal>.
172	Found 8-bit updown counter for signal <fifo_counter>.
173	Found 8-bit up counter for signal <pop_address_counter>.
174	Found 8-bit up counter for signal <push_address_counter>.
175	Summary:
176	inferred 1 Finite State Machine(s).
177	inferred 3 Counter(s).
178	inferred 8 D-type flip-flop(s).
179	Unit <FIFO_256_FWFT> synthesized.
180
181
182	Synthesizing Unit <INPUT_PORT_MODULE>.
183	Related source file is "C:/Documents and Settings/GENERAL/Bureau/GENERIC_16_16/INPUT_PORT_MODULE.vhd".
184	Found finite state machine <FSM_1> for signal <pop_state>.
185	-----------------------------------------------------------------------
186	\| States \| 4 \|
187	\| Transitions \| 9 \|
188	\| Inputs \| 4 \|
189	\| Outputs \| 5 \|
190	\| Clock \| clk (rising_edge) \|
191	\| Reset \| reset_signal (positive) \|
192	\| Reset type \| synchronous \|
193	\| Reset State \| state0 \|
194	\| Power Up State \| state0 \|
195	\| Encoding \| automatic \|
196	\| Implementation \| LUT \|
197	-----------------------------------------------------------------------
198	Found 8-bit register for signal <data_counter>.
199	Found 8-bit subtractor for signal <data_counter$share0000> created at line 434.
200	Found 1-bit register for signal <empty_latch>.
201	Found 8-bit register for signal <pipeline_latch>.
202	Found 5-bit comparator greater for signal <port_granted$cmp_gt0000> created at line 110.
203	Found 4-bit register for signal <request_latch>.
204	Summary:
205	inferred 1 Finite State Machine(s).
206	inferred 21 D-type flip-flop(s).
207	inferred 1 Adder/Subtractor(s).
208	inferred 1 Comparator(s).
209	Unit <INPUT_PORT_MODULE> synthesized.
210
211	INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
212
213	=========================================================================
214	HDL Synthesis Report
215
216	Macro Statistics
217	# RAMs : 1
218	256x8-bit dual-port RAM : 1
219	# Adders/Subtractors : 1
220	8-bit subtractor : 1
221	# Counters : 3
222	8-bit up counter : 2
223	8-bit updown counter : 1
224	# Registers : 6
225	1-bit register : 1
226	4-bit register : 1
227	8-bit register : 4
228	# Comparators : 1
229	5-bit comparator greater : 1
230
231	=========================================================================
232
233	=========================================================================
234	* Advanced HDL Synthesis *
235	=========================================================================
236
237	Analyzing FSM <FSM_1> for best encoding.
238	Choose code 2 with characteristics nb_luts=8,nb_literals=21,nb_ffs=2,depth=2 ...
239	Optimizing FSM <pop_state/FSM> on signal <pop_state[1:2]> with gray encoding.
240	--------------------
241	State \| Encoding
242	--------------------
243	state0 \| 00
244	state1 \| 01
245	state2 \| 11
246	state3 \| 10
247	--------------------
248	Analyzing FSM <FSM_0> for best encoding.
249	Choose code 7 with characteristics nb_luts=5,nb_literals=16,nb_ffs=2,depth=2 ...
250	Optimizing FSM <INPUT_PORT_FIFO/fwft_fsm_state/FSM> on signal <fwft_fsm_state[1:2]> with user encoding.
251	--------------------
252	State \| Encoding
253	--------------------
254	state0 \| 00
255	state1 \| 01
256	state2 \| 10
257	--------------------
258
259	Synthesizing (advanced) Unit <RAM_256>.
260	INFO:Xst - The RAM <Mram_RAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <dob>
261	-----------------------------------------------------------------------
262	\| ram_type \| Block \| \|
263	-----------------------------------------------------------------------
264	\| Port A \|
265	\| aspect ratio \| 256-word x 8-bit \| \|
266	\| mode \| read-first \| \|
267	\| clkA \| connected to signal <clka> \| rise \|
268	\| weA \| connected to signal <wea> \| high \|
269	\| addrA \| connected to signal <addra> \| \|
270	\| diA \| connected to signal <dia> \| \|
271	-----------------------------------------------------------------------
272	\| optimization \| speed \| \|
273	-----------------------------------------------------------------------
274	\| Port B \|
275	\| aspect ratio \| 256-word x 8-bit \| \|
276	\| mode \| write-first \| \|
277	\| clkB \| connected to signal <clkb> \| rise \|
278	\| addrB \| connected to signal <addrb> \| \|
279	\| doB \| connected to signal <dob> \| \|
280	-----------------------------------------------------------------------
281	\| optimization \| speed \| \|
282	-----------------------------------------------------------------------
283	Unit <RAM_256> synthesized (advanced).
284
285	=========================================================================
286	Advanced HDL Synthesis Report
287
288	Macro Statistics
289	# FSMs : 2
290	# RAMs : 1
291	256x8-bit dual-port block RAM : 1
292	# Adders/Subtractors : 1
293	8-bit subtractor : 1
294	# Counters : 3
295	8-bit up counter : 2
296	8-bit updown counter : 1
297	# Registers : 29
298	Flip-Flops : 29
299	# Comparators : 1
300	5-bit comparator greater : 1
301
302	=========================================================================
303
304	=========================================================================
305	* Low Level Synthesis *
306	=========================================================================
307
308	Optimizing unit <INPUT_PORT_MODULE> ...
309
310	Optimizing unit <FIFO_256_FWFT> ...
311
312	Mapping all equations...
313	Building and optimizing final netlist ...
314	Found area constraint ratio of 100 (+ 5) on block INPUT_PORT_MODULE, actual ratio is 0.
315
316	Final Macro Processing ...
317
318	=========================================================================
319	Final Register Report
320
321	Macro Statistics
322	# Registers : 57
323	Flip-Flops : 57
324
325	=========================================================================
326
327	=========================================================================
328	* Partition Report *
329	=========================================================================
330
331	Partition Implementation Status
332	-------------------------------
333
334	No Partitions were found in this design.
335
336	-------------------------------
337
338	=========================================================================
339	* Final Report *
340	=========================================================================
341	Final Results
342	RTL Top Level Output File Name : INPUT_PORT_MODULE.ngr
343	Top Level Output File Name : INPUT_PORT_MODULE
344	Output Format : NGC
345	Optimization Goal : Speed
346	Keep Hierarchy : NO
347
348	Design Statistics
349	# IOs : 31
350
351	Cell Usage :
352	# BELS : 142
353	# GND : 1
354	# INV : 2
355	# LUT1 : 14
356	# LUT2 : 4
357	# LUT3 : 20
358	# LUT3_D : 1
359	# LUT3_L : 2
360	# LUT4 : 44
361	# LUT4_D : 5
362	# LUT4_L : 2
363	# MUXCY : 21
364	# MUXF5 : 1
365	# VCC : 1
366	# XORCY : 24
367	# FlipFlops/Latches : 57
368	# FDE : 8
369	# FDR : 3
370	# FDRE : 37
371	# FDRS : 9
372	# RAMS : 1
373	# RAMB16_S9_S9 : 1
374	# Clock Buffers : 1
375	# BUFGP : 1
376	# IO Buffers : 30
377	# IBUF : 14
378	# OBUF : 16
379	=========================================================================
380
381	Device utilization summary:
382	---------------------------
383
384	Selected Device : 3s1200efg320-4
385
386	Number of Slices: 49 out of 8672 0%
387	Number of Slice Flip Flops: 57 out of 17344 0%
388	Number of 4 input LUTs: 94 out of 17344 0%
389	Number of IOs: 31
390	Number of bonded IOBs: 31 out of 250 12%
391	Number of BRAMs: 1 out of 28 3%
392	Number of GCLKs: 1 out of 24 4%
393
394	---------------------------
395	Partition Resource Summary:
396	---------------------------
397
398	No Partitions were found in this design.
399
400	---------------------------
401
402
403	=========================================================================
404	TIMING REPORT
405
406	NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
407	FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
408	GENERATED AFTER PLACE-and-ROUTE.
409
410	Clock Information:
411	------------------
412	-----------------------------------+------------------------+-------+
413	Clock Signal \| Clock buffer(FF name) \| Load \|
414	-----------------------------------+------------------------+-------+
415	clk \| BUFGP \| 58 \|
416	-----------------------------------+------------------------+-------+
417
418	Asynchronous Control Signals Information:
419	----------------------------------------
420	No asynchronous control signals found in this design
421
422	Timing Summary:
423	---------------
424	Speed Grade: -4
425
426	Minimum period: 7.226ns (Maximum Frequency: 138.389MHz)
427	Minimum input arrival time before clock: 9.258ns
428	Maximum output required time after clock: 7.556ns
429	Maximum combinational path delay: 8.635ns
430
431	Timing Detail:
432	--------------
433	All values displayed in nanoseconds (ns)
434
435	=========================================================================
436	Timing constraint: Default period analysis for Clock 'clk'
437	Clock period: 7.226ns (frequency: 138.389MHz)
438	Total number of paths / destination ports: 1824 / 119
439	-------------------------------------------------------------------------
440	Delay: 7.226ns (Levels of Logic = 11)
441	Source: pop_state_FSM_FFd1 (FF)
442	Destination: INPUT_PORT_FIFO/fifo_counter_7 (FF)
443	Source Clock: clk rising
444	Destination Clock: clk rising
445
446	Data Path: pop_state_FSM_FFd1 to INPUT_PORT_FIFO/fifo_counter_7
447	Gate Net
448	Cell:in->out fanout Delay Delay Logical Name (Net Name)
449	---------------------------------------- ------------
450	FDRE:C->Q 18 0.591 1.103 pop_state_FSM_FFd1 (pop_state_FSM_FFd1)
451	LUT4_D:I2->O 1 0.704 0.455 INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14)
452	LUT3:I2->O 14 0.704 1.035 INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal)
453	LUT3:I2->O 1 0.704 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>)
454	MUXCY:S->O 1 0.464 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>)
455	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>)
456	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>)
457	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>)
458	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>)
459	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>)
460	MUXCY:CI->O 0 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>)
461	XORCY:CI->O 1 0.804 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>)
462	FDRE:D 0.308 INPUT_PORT_FIFO/fifo_counter_7
463	----------------------------------------
464	Total 7.226ns (4.633ns logic, 2.593ns route)
465	(64.1% logic, 35.9% route)
466
467	=========================================================================
468	Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
469	Total number of paths / destination ports: 528 / 134
470	-------------------------------------------------------------------------
471	Offset: 9.258ns (Levels of Logic = 13)
472	Source: grant<1> (PAD)
473	Destination: INPUT_PORT_FIFO/fifo_counter_7 (FF)
474	Destination Clock: clk rising
475
476	Data Path: grant<1> to INPUT_PORT_FIFO/fifo_counter_7
477	Gate Net
478	Cell:in->out fanout Delay Delay Logical Name (Net Name)
479	---------------------------------------- ------------
480	IBUF:I->O 1 1.218 0.595 grant_1_IBUF (grant_1_IBUF)
481	LUT4:I0->O 16 0.704 1.209 port_granted1 (port_granted)
482	LUT4_D:I0->O 1 0.704 0.455 INPUT_PORT_FIFO/rd_en_signal1_SW5 (N14)
483	LUT3:I2->O 14 0.704 1.035 INPUT_PORT_FIFO/rd_en_signal1 (INPUT_PORT_FIFO/rd_en_signal)
484	LUT3:I2->O 1 0.704 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_lut<0>)
485	MUXCY:S->O 1 0.464 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<0>)
486	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<1>)
487	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<2>)
488	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<3>)
489	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<4>)
490	MUXCY:CI->O 1 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<5>)
491	MUXCY:CI->O 0 0.059 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6> (INPUT_PORT_FIFO/Mcount_fifo_counter_cy<6>)
492	XORCY:CI->O 1 0.804 0.000 INPUT_PORT_FIFO/Mcount_fifo_counter_xor<7> (INPUT_PORT_FIFO/Result<7>)
493	FDRE:D 0.308 INPUT_PORT_FIFO/fifo_counter_7
494	----------------------------------------
495	Total 9.258ns (5.964ns logic, 3.294ns route)
496	(64.4% logic, 35.6% route)
497
498	=========================================================================
499	Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
500	Total number of paths / destination ports: 53 / 16
501	-------------------------------------------------------------------------
502	Offset: 7.556ns (Levels of Logic = 3)
503	Source: pop_state_FSM_FFd1 (FF)
504	Destination: request<4> (PAD)
505	Source Clock: clk rising
506
507	Data Path: pop_state_FSM_FFd1 to request<4>
508	Gate Net
509	Cell:in->out fanout Delay Delay Logical Name (Net Name)
510	---------------------------------------- ------------
511	FDRE:C->Q 18 0.591 1.243 pop_state_FSM_FFd1 (pop_state_FSM_FFd1)
512	LUT4:I0->O 4 0.704 0.622 request_decoder_and00001 (request_decoder_and0000)
513	LUT3:I2->O 1 0.704 0.420 request_decoder<4>1 (request_4_OBUF)
514	OBUF:I->O 3.272 request_4_OBUF (request<4>)
515	----------------------------------------
516	Total 7.556ns (5.271ns logic, 2.285ns route)
517	(69.8% logic, 30.2% route)
518
519	=========================================================================
520	Timing constraint: Default path analysis
521	Total number of paths / destination ports: 8 / 2
522	-------------------------------------------------------------------------
523	Delay: 8.635ns (Levels of Logic = 4)
524	Source: grant<1> (PAD)
525	Destination: data_out_pulse (PAD)
526
527	Data Path: grant<1> to data_out_pulse
528	Gate Net
529	Cell:in->out fanout Delay Delay Logical Name (Net Name)
530	---------------------------------------- ------------
531	IBUF:I->O 1 1.218 0.595 grant_1_IBUF (grant_1_IBUF)
532	LUT4:I0->O 16 0.704 1.209 port_granted1 (port_granted)
533	LUT4:I0->O 11 0.704 0.933 data_out_pulse1 (data_out_pulse_OBUF)
534	OBUF:I->O 3.272 data_out_pulse_OBUF (data_out_pulse)
535	----------------------------------------
536	Total 8.635ns (5.898ns logic, 2.737ns route)
537	(68.3% logic, 31.7% route)
538
539	=========================================================================
540
541
542	Total REAL time to Xst completion: 10.00 secs
543	Total CPU time to Xst completion: 9.84 secs
544
545	-->
546
547	Total memory usage is 137348 kilobytes
548
549	Number of errors : 0 ( 0 filtered)
550	Number of warnings : 0 ( 0 filtered)
551	Number of infos : 2 ( 0 filtered)
552

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