[24] | 1 | |
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| 2 | ---------------------------------------------------------------------------------- |
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| 3 | -- Company: |
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| 4 | -- Engineer: |
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| 5 | -- |
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| 6 | -- Create Date: 09:29:48 04/18/2011 |
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| 7 | -- Design Name: |
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| 8 | -- Module Name: OUTPUT_PORT_MODULE - Behavioral_description |
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| 9 | -- Project Name: |
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| 10 | -- Target Devices: |
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| 11 | -- Tool versions: |
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| 12 | -- Description: |
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| 13 | -- cette version du module de sortie se limite à une instance du fifo ordinaire |
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| 14 | -- les données son emise en sortie à chaque cycle d'horloge |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | ---------------------------------------------------------------------------------- |
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| 22 | library IEEE; |
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| 23 | use IEEE.STD_LOGIC_1164.ALL; |
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| 24 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | Library NocLib; |
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| 27 | use NocLib.CoreTypes.all; |
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| 28 | ---- Uncomment the following library declaration if instantiating |
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| 29 | ---- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity OUTPUT_PORT_MODULE is |
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| 34 | Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 35 | reset : in STD_LOGIC; |
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| 36 | clk : in STD_LOGIC; |
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| 37 | wr_en : in STD_LOGIC; |
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| 38 | data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 39 | fifo_full : out std_logic; |
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| 40 | data_avalaible : out std_logic; |
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| 41 | rd_out_en : in STD_LOGIC); |
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| 42 | end OUTPUT_PORT_MODULE; |
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| 43 | |
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| 44 | architecture Behavioral_description of OUTPUT_PORT_MODULE is |
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| 45 | -- declaration du FIFO 64 octets |
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| 46 | component FIFO_256_FWFT |
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| 47 | port ( |
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| 48 | clk: IN std_logic; |
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| 49 | din: IN std_logic_VECTOR(Word-1 downto 0); |
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| 50 | rd_en: IN std_logic; |
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| 51 | srst: IN std_logic; |
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| 52 | wr_en: IN std_logic; |
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| 53 | dout: OUT std_logic_VECTOR(Word-1 downto 0); |
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| 54 | empty: OUT std_logic; |
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| 55 | full: OUT std_logic); |
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| 56 | end component; |
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| 57 | --definition du type etat pour les fsm |
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| 58 | signal empty_signal : std_logic; |
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| 59 | begin |
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| 60 | -- instantiation du FIFO_64 |
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| 61 | OUTPUT_PORT_FIFO : FIFO_256_FWFT |
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| 62 | port map ( |
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| 63 | clk => clk, |
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| 64 | din => data_in, |
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| 65 | rd_en => rd_out_en, |
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| 66 | srst => reset, |
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| 67 | wr_en => wr_en, |
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| 68 | dout => data_out, |
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| 69 | empty => empty_signal, |
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| 70 | full => fifo_full); |
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| 71 | |
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| 72 | data_avalaible <= not empty_signal; |
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| 73 | |
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| 74 | end Behavioral_description; |
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| 75 | |
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