[24] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 17:03:41 10/22/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Proto_receiv - ReceiveProto |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | USE ieee.numeric_std.ALL; |
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| 23 | use work.CoreTypes.all; |
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| 24 | -- Uncomment the following library declaration if using |
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| 25 | -- arithmetic functions with Signed or Unsigned values |
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| 26 | --use IEEE.NUMERIC_STD.ALL; |
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| 27 | |
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| 28 | -- Uncomment the following library declaration if instantiating |
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| 29 | -- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity Proto_receiv is |
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| 34 | generic (sizemem : natural := 64); |
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| 35 | port ( |
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| 36 | clk,reset : in std_logic; |
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| 37 | fifo_empty,fifo_full : in std_logic; |
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| 38 | rcv_start : in std_logic; --début de la réception |
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| 39 | rcv_ack :in std_logic; -- acquittement de la réception |
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| 40 | rcv_comp : out std_logic; -- fin de la réception |
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| 41 | pop : out std_logic:='0'; |
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| 42 | fifo_out : in std_logic_vector(Word-1 downto 0); |
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| 43 | mem :out memory(0 to sizemem-1)); |
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| 44 | end Proto_receiv; |
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| 45 | |
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| 46 | architecture ReceiveProto of Proto_receiv is |
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| 47 | type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end); |
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| 48 | |
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| 49 | signal spush,spop : std_logic:='0'; |
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| 50 | SIGNAL data_in: std_logic_vector(7 downto 0); |
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| 51 | signal etrec :typ_receiv; |
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| 52 | begin |
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| 53 | |
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| 54 | proc_receiv : process (clk,reset) |
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| 55 | variable dlen,i: natural range 0 to 255 :=0; |
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| 56 | |
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| 57 | begin |
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| 58 | if reset='1' then |
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| 59 | etrec<=r_wait; |
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| 60 | |
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| 61 | else |
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| 62 | if rising_edge(clk) then -- le process s'exécute sur chaque front |
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| 63 | -- montant de l'horloge |
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| 64 | case etrec is |
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| 65 | when r_wait => |
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| 66 | |
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| 67 | i:=0; |
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| 68 | if fifo_empty='0' and rcv_start='1' then |
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| 69 | |
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| 70 | etrec<=r_head; |
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| 71 | mem(0)<=fifo_out; |
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| 72 | |
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| 73 | end if; |
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| 74 | when r_head => |
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| 75 | mem(0)<=fifo_out; --l'en-tête |
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| 76 | |
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| 77 | etrec<=r_len; |
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| 78 | |
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| 79 | |
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| 80 | when r_len => |
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| 81 | dlen:=to_integer(unsigned(fifo_out)); |
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| 82 | mem(1)<=fifo_out; -- la longueur |
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| 83 | etrec<=r_data; |
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| 84 | |
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| 85 | i:=1; |
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| 86 | |
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| 87 | when r_data => |
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| 88 | if fifo_empty='0' then |
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| 89 | if i<dlen-3 then |
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| 90 | i:=i+1; |
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| 91 | mem(i)<=fifo_out; |
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| 92 | |
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| 93 | |
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| 94 | else |
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| 95 | etrec<=r_pulse; |
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| 96 | |
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| 97 | mem(i+1)<=fifo_out; |
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| 98 | end if; |
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| 99 | -- time out à prévoir ici |
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| 100 | end if; |
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| 101 | when r_pulse => |
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| 102 | etrec<=r_end; |
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| 103 | |
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| 104 | when r_end => |
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| 105 | if rcv_ack='1' then |
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| 106 | etrec<=r_wait; |
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| 107 | end if; |
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| 108 | |
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| 109 | when others => |
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| 110 | |
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| 111 | |
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| 112 | etrec<=r_wait; |
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| 113 | end case; |
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| 114 | end if; |
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| 115 | end if; |
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| 116 | end process; |
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| 117 | |
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| 118 | pop<=spop; |
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| 119 | |
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| 120 | rec_value : process (etrec) |
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| 121 | begin |
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| 122 | case etrec is |
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| 123 | when r_wait => |
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| 124 | spop<='0'; |
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| 125 | rcv_comp<='0'; |
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| 126 | when r_head => |
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| 127 | |
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| 128 | spop<='1'; |
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| 129 | rcv_comp<='0'; |
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| 130 | -- when r_sync => |
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| 131 | -- spop<='1'; |
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| 132 | -- rcv_comp<='0'; |
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| 133 | when r_len => |
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| 134 | spop<='1'; |
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| 135 | when r_data => |
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| 136 | spop<='1'; |
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| 137 | when r_pulse => |
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| 138 | spop<='0'; |
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| 139 | rcv_comp<='1'; |
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| 140 | when r_end => |
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| 141 | spop<='0'; |
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| 142 | rcv_comp<='1'; |
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| 143 | when others => |
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| 144 | spop<='0'; |
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| 145 | rcv_comp<='0'; |
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| 146 | end case; |
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| 147 | end process; |
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| 148 | end ReceiveProto; |
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| 149 | |
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