[24] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL GEL EN 5 |
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| 4 | -- |
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| 5 | -- Create Date: 18:54:08 04/19/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: RAM_64 - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: SYNTHESE d'une RAM 256 octet par inferation |
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| 12 | -- la ram possède un port d'écriture et un port de lecture |
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| 13 | -- le port primaire est à lecture et ecrite et le port secondaire à lecture seule |
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| 14 | -- |
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| 15 | -- Dependencies: |
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| 16 | -- |
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| 17 | -- Revision: |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | ---------------------------------------------------------------------------------- |
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| 22 | library IEEE; |
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| 23 | use IEEE.STD_LOGIC_1164.ALL; |
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| 24 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | --Library NocLib; |
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| 27 | --use NocLib.CoreTypes.all; |
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| 28 | use work.CoreTypes.all; |
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| 29 | ---- Uncomment the following library declaration if instantiating |
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| 30 | ---- any Xilinx primitives in this code. |
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| 31 | --library UNISIM; |
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| 32 | --use UNISIM.VComponents.all; |
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| 33 | |
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| 34 | entity RAM_256 is |
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| 35 | Port ( clka, clkb : in std_logic; |
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| 36 | wea : in std_logic; |
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| 37 | ena, enb : in std_logic; |
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| 38 | addra, addrb : in std_logic_vector(Word-1 downto 0); |
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| 39 | dia : in std_logic_vector(Word-1 downto 0); |
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| 40 | dob : out std_logic_vector(Word-1 downto 0)); |
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| 41 | end RAM_256; |
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| 42 | |
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| 43 | architecture Behavioral of RAM_256 is |
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| 44 | type ram_type is array (255 downto 0) of std_logic_vector (Word-1 downto 0); |
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| 45 | signal RAM: ram_type; |
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| 46 | begin |
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| 47 | process (clka) |
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| 48 | begin |
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| 49 | if clka'event and clka = '1' then |
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| 50 | if ena = '1' then |
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| 51 | if wea = '1' then |
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| 52 | RAM(conv_integer(addra)) <= dia; |
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| 53 | end if; |
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| 54 | end if; |
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| 55 | end if; |
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| 56 | end process; |
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| 57 | |
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| 58 | process (clkb) |
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| 59 | begin |
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| 60 | if clkb'event and clkb = '1' then |
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| 61 | if enb = '1' then |
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| 62 | dob <= RAM(conv_integer(addrb)) ; |
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| 63 | end if; |
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| 64 | end if; |
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| 65 | end process; |
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| 66 | |
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| 67 | end Behavioral; |
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| 68 | |
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