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[24] | 1 | |
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| 2 | -- VHDL Instantiation Created from source file Scheduler4_4.vhd -- 13:38:35 06/19/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT Scheduler4_4 |
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| 10 | PORT( |
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| 11 | Request : IN std_logic_vector(16 downto 1); |
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| 12 | Fifo_full : IN std_logic_vector(4 downto 1); |
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| 13 | clk : IN std_logic; |
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| 14 | reset : IN std_logic; |
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| 15 | priority_rotation : IN std_logic_vector(4 downto 1); |
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| 16 | port_grant : OUT std_logic_vector(16 downto 1) |
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| 17 | ); |
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| 18 | END COMPONENT; |
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| 19 | |
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| 20 | Inst_Scheduler4_4: Scheduler4_4 PORT MAP( |
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| 21 | Request => , |
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| 22 | Fifo_full => , |
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| 23 | clk => , |
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| 24 | reset => , |
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| 25 | priority_rotation => , |
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| 26 | port_grant => |
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| 27 | ); |
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| 28 | |
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| 29 | |
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