source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.01/FIFO_DP.vhd

Last change on this file was 22, checked in by rolagamo, 12 years ago
File size: 2.2 KB
Line 
1----------------------------------------------------------------------------------
2-- Company:
3-- Engineer:
4--
5-- Create Date:    16:32:59 10/23/2012
6-- Design Name:
7-- Module Name:    FIFO_DP - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description:
12--
13-- Dependencies:
14--
15-- Revision:
16-- Revision 0.01 - File Created
17-- Additional Comments:
18--
19----------------------------------------------------------------------------------
20
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25
26entity fifo_dp is
27GENERIC
28(
29ADDRESS_WIDTH : integer:=8;---8 bit
30DATA_WIDTH : integer:=8 ---8 bit
31);
32
33port ( clk : in std_logic;
34reset : in std_logic;
35enr : in std_logic; --enable read,should be '0' when not in use.
36enw : in std_logic; --enable write,should be '0' when not in use.
37dataout : out std_logic_vector(DATA_WIDTH-1 downto 0); --output data
38datain : in std_logic_vector (DATA_WIDTH-1 downto 0); --input data
39empty : out std_logic; --set as '1' when the queue is empty
40err : out std_logic;
41full : out std_logic --set as '1' when the queue is full
42);
43end fifo;
44
45architecture Behavioral of fifo_dp is
46
47type memory_type is array (0 to ((2**ADDRESS_WIDTH)-1)) of std_logic_vector(DATA_WIDTH-1 downto 0);
48
49
50-----distributed-------
51signal memory : memory_type ;-- :=(others => (others => '0')); --memory for queue.-----
52signal readptr,writeptr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); --read and write pointers.
53signal full0 : std_logic;
54signal empty0 : std_logic;
55
56begin
57full <= full0;
58empty <= empty0; 
59
60fifo0: process(clk,reset)
61begin
62if reset='1' then
63
64readptr <= (others => '0');
65writeptr <= (others => '0');
66empty0 <='1';
67full0<='0';
68err<='0';
69
70
71elsif rising_edge(clk) then 
72
73if (writeptr + '1' = readptr) then 
74full0<='1';
75else
76full0<='0';
77end if ;
78
79if (readptr = writeptr ) then 
80empty0<='1';
81else
82empty0<='0';
83end if ; 
84
85if (empty0='0' and enr='1') or (full0='0' and enw='1') then 
86err<='1';
87end if ; 
88
89if enw='1' and full0='0' then 
90memory (conv_integer(writeptr)) <= datain ;
91writeptr <= writeptr + '1' ;
92end if ; 
93
94if enr='1' and empty0='0' then 
95dataout <= memory (conv_integer(readptr));
96readptr <= readptr + '1' ;
97end if ; 
98
99end if; 
100
101end process;
102end Behavioral;
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