GENERIC_16_16 Project Status (06/19/2011 - 19:25:38)
Project File:	GENERIC_16_16.ise	Implementation State:	Synthesized
Module Name:	INPUT_PORT_MODULE	Errors:
Target Device:	xc3s1200e-4fg320	Warnings:
Product Version:	ISE 11.1	Routing Results:
Design Goal:	Balanced	Timing Constraints:
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:

 

Device Utilization Summary (estimated values)				[-]
Logic Utilization	Used	Available	Utilization
Number of Slices	49	8672	0%
Number of Slice Flip Flops	57	17344	0%
Number of 4 input LUTs	94	17344	0%
Number of bonded IOBs	31	250	12%
Number of BRAMs	1	28	3%
Number of GCLKs	1	24	4%

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	dim. 19. juin 14:27:18 2011
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated

Date Generated: 06/19/2011 - 19:26:32