source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.02/SCHEDULER3_3.VHD

Last change on this file was 22, checked in by rolagamo, 12 years ago
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1---------------------------------------------------------------------------------
2-- Company:
3-- Engineer: KIEGAING EMMANUEL GEL EN 5
4--
5-- Create Date:    03:56:34 05/06/2011
6-- Design Name:
7-- Module Name:    Sheduler - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Module de l'ordonnanceur du switch crossbar
12-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25--use Work.Sheduler_package.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31entity Scheduler3_3 is
32    Port ( Request : in  STD_LOGIC_VECTOR (9 downto 1);
33                   Fifo_full : in STD_LOGIC_VECTOR (3 downto 1);
34           clk : in  STD_LOGIC;
35           reset : in  STD_LOGIC;
36            priority_rotation : in  STD_LOGIC_VECTOR (3 downto 1);
37           port_grant : out  STD_LOGIC_VECTOR (9 downto 1));
38end Scheduler3_3;
39
40architecture Behavioral of Scheduler3_3 is
41--Declaration du types
42--tableau de signaux de connexion des cellules arbitres
43TYPE C_Bar_Signal_Array IS ARRAY(5 downto 1) of STD_LOGIC_VECTOR(3 downto 1);
44-- declaration du composant cellule d'arbitrage
45Component Arbiter
46  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
47        Grant,East,South : out  STD_LOGIC );
48End Component;--Signaux de connexion des cellues
49SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north
50SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west
51SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
52SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
53SIGNAL Signal_priority  : STD_LOGIC_VECTOR (5 DOWNTO 1);--signal pour la connection des vecteur de priorité
54SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest
55 signal grant_latch : std_logic_vector(9 downto 1);
56 signal priority_rotation_en : std_logic;
57 signal Grant,req_grant :  std_logic_vector(9 downto 1);
58 begin
59
60--validation de la rotation de priorité lorsque aucun port n'emet
61 req_grant<=(request and grant_latch);
62 priority_rotation_en <= '1' when unsigned(priority_rotation) = 7 else  '0';
63--latch servant qui memorise le signal grant pendant a transmission
64grant_latch_process : process(clk)
65 begin
66  if rising_edge(clk) then
67   if reset = '1' then
68                grant_latch <= (others => '0');
69         elsif priority_rotation_en = '1' then
70           grant_latch <= Grant;
71   end if;
72   end if;
73 end process;
74 port_grant <= grant_latch;
75 Grant(1)  <= Signal_grant(1)(1) or Signal_grant(4)(1); --  Grant(1,1)
76Grant(2)  <= Signal_grant(2)(2) or Signal_grant(5)(2); --  Grant(1,2)
77Grant(3)  <= Signal_grant(3)(3) ;                      --  Grant(1,3)
78Grant(4)  <= Signal_grant(2)(1) or Signal_grant(5)(1); --  Grant(2,1)
79Grant(5)  <= Signal_grant(3)(2) ;                      --  Grant(2,2)
80Grant(6)  <= Signal_grant(1)(3) or Signal_grant(4)(3); --  Grant(2,3)
81Grant(7)  <= Signal_grant(3)(1) ;                      --  Grant(3,1)
82Grant(8)  <= Signal_grant(1)(2) or Signal_grant(4)(2); --  Grant(3,2)
83Grant(9)  <= Signal_grant(2)(3) or Signal_grant(5)(3); --  Grant(3,3)
84High <= '1';
85
86----instantiations des cellules arbitres et interconnection
87
88-------------------------- Diagonale n° 1
89
90
91Arbiter_1_1 : Arbiter
92
93PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(1), 
94South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1));
95
96Arbiter_1_2 : Arbiter
97
98PORT MAP (Request => Request(8), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(2), 
99South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2));
100
101Arbiter_1_3 : Arbiter
102
103PORT MAP (Request => Request(6), North => High, West => High, P => Signal_priority(5), Fifo_full => Fifo_full(3), 
104South => south_2_north(1)(3), East => east_2_west(1)(3) , Grant => Signal_grant(1)(3));
105
106-------------------------- Diagonale n° 2
107
108
109Arbiter_2_1 : Arbiter
110
111PORT MAP (Request => Request(4), North => south_2_north(1)(1), West => east_2_west(1)(3), P => Signal_priority(4), Fifo_full => Fifo_full(1), 
112South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1));
113
114Arbiter_2_2 : Arbiter
115
116PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(4), Fifo_full => Fifo_full(2), 
117South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2));
118
119Arbiter_2_3 : Arbiter
120
121PORT MAP (Request => Request(9), North => south_2_north(1)(3), West => east_2_west(1)(2), P => Signal_priority(4), Fifo_full => Fifo_full(3), 
122South => south_2_north(2)(3), East => east_2_west(2)(3) , Grant => Signal_grant(2)(3));
123
124-------------------------- Diagonale n° 3
125
126
127Arbiter_3_1 : Arbiter
128
129PORT MAP (Request => Request(7), North => south_2_north(2)(1), West => east_2_west(2)(3), P => Signal_priority(3), Fifo_full => Fifo_full(1), 
130South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1));
131
132Arbiter_3_2 : Arbiter
133
134PORT MAP (Request => Request(5), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(3), Fifo_full => Fifo_full(2), 
135South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2));
136
137Arbiter_3_3 : Arbiter
138
139PORT MAP (Request => Request(3), North => south_2_north(2)(3), West => east_2_west(2)(2), P => Signal_priority(3), Fifo_full => Fifo_full(3), 
140South => south_2_north(3)(3), East => east_2_west(3)(3) , Grant => Signal_grant(3)(3));
141
142-------------------------- Diagonale n° 4
143
144
145Arbiter_4_1 : Arbiter
146
147PORT MAP (Request => Request(1), North => south_2_north(3)(1), West => east_2_west(3)(3), P => Signal_priority(2), Fifo_full => Fifo_full(1), 
148South => south_2_north(4)(1), East => east_2_west(4)(1) , Grant => Signal_grant(4)(1));
149
150Arbiter_4_2 : Arbiter
151
152PORT MAP (Request => Request(8), North => south_2_north(3)(2), West => east_2_west(3)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), 
153South => south_2_north(4)(2), East => east_2_west(4)(2) , Grant => Signal_grant(4)(2));
154
155Arbiter_4_3 : Arbiter
156
157PORT MAP (Request => Request(6), North => south_2_north(3)(3), West => east_2_west(3)(2), P => Signal_priority(2), Fifo_full => Fifo_full(3), 
158South => south_2_north(4)(3), East => east_2_west(4)(3) , Grant => Signal_grant(4)(3));
159
160-------------------------- Diagonale n° 5
161
162
163Arbiter_5_1 : Arbiter
164
165PORT MAP (Request => Request(4), North => south_2_north(4)(1), West => east_2_west(4)(3), P => Signal_priority(1), Fifo_full => Fifo_full(1), 
166South => south_2_north(5)(1), East => east_2_west(5)(1) , Grant => Signal_grant(5)(1));
167
168Arbiter_5_2 : Arbiter
169
170PORT MAP (Request => Request(2), North => south_2_north(4)(2), West => east_2_west(4)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), 
171South => south_2_north(5)(2), East => east_2_west(5)(2) , Grant => Signal_grant(5)(2));
172
173Arbiter_5_3 : Arbiter
174
175PORT MAP (Request => Request(9), North => south_2_north(4)(3), West => east_2_west(4)(2), P => Signal_priority(1), Fifo_full => Fifo_full(3), 
176South => south_2_north(5)(3), East => east_2_west(5)(3) , Grant => Signal_grant(5)(3));
177
178
179--processus permettant de roter la priorité des diagonales à chaque front d'horloge
180 -- rotation round robin
181         round_robin : process(clk)
182        begin
183                if rising_edge(clk) then
184                 if reset ='1' then
185                    Signal_priority <= "11100";
186                  elsif priority_rotation_en = '1' then
187                    case Signal_priority is
188                       when "11100" => Signal_priority <= "01110";
189                       when "01110" => Signal_priority <= "00111";
190                       when "00111" => Signal_priority <= "11100";
191                       when others    => Signal_priority <= "11100";
192                  end case;
193                 end if;
194             end if;
195         end process;
196
197end Behavioral;
198
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