[69] | 1 | -- Package File Template |
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| 2 | -- |
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| 3 | -- Purpose: This package defines supplemental types, subtypes, |
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| 4 | -- constants, and components |
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| 5 | |
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| 6 | |
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| 7 | library IEEE; |
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| 8 | use IEEE.STD_LOGIC_1164.all; |
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| 9 | use IEEE.numeric_std.all; |
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| 10 | package CoreTypes is |
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| 11 | CONSTANT Word :POSITIVE:= 8; |
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| 12 | CONSTANT ADRLEN:POSITIVE:=16; |
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| 13 | CONSTANT LZFILL :std_logic_vector(2*Word-ADRLEN to 0):=(others=>'0');--indique le nombre de zero à utiliser pour completer le bus de données lorsque la longueur restante du bus d'adresse est inférueure à la largeur du bus de données |
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| 14 | CONSTANT IADR0 : NATURAL :=2; --Adresse basse de l'instruction |
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| 15 | CONSTANT IADR1 : natural :=3; |
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| 16 | CONSTANT CORE_BASE_ADR :natural range 0 to 65535:=4096; |
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| 17 | CONSTANT CORE_UPPER_ADR : natural range 0 to 255:=16; |
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| 18 | CONSTANT CORE_GET_ADR:natural:=CORE_BASE_ADR+526; |
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| 19 | CONSTANT CORE_PUT_ADR :natural:=CORE_BASE_ADR+516; |
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| 20 | CONSTANT core_INIT_ADR : natural:=CORE_BASE_ADR+512; |
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| 21 | CONSTANT CORE_WCREATE_ADR : natural := CORE_BASE_ADR+536; |
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| 22 | CONSTANT CORE_WCOMPL_ADR : natural := CORE_BASE_ADR+546; |
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| 23 | CONSTANT CORE_WPOST_ADR : natural := CORE_BASE_ADR+556; |
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| 24 | CONSTANT CORE_WWAIT_ADR : natural := CORE_BASE_ADR+566; |
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| 25 | CONSTANT CORE_SPAWN_ADR : natural := CORE_BASE_ADR+576; |
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| 26 | CONSTANT CORE_Rank2port_BASE :NATURAL:=52; |
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| 27 | CONSTANT CORE_RANK_ADR : NATURAL:=CORE_BASE_ADR+CORE_Rank2Port_Base; |
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| 28 | CONSTANT WIN0_ADR :natural :=4; |
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| 29 | CONSTANT WIN1_ADR :natural :=14; |
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| 30 | CONSTANT WIN2_ADR :natural :=24; |
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| 31 | CONSTANT WIN3_ADR :natural :=34; |
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| 32 | CONSTANT GETPORTID : std_logic_vector(3 downto 0):="0001"; |
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| 33 | |
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| 34 | type Typ_PortIO is |
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| 35 | array(natural range <>) of std_logic_vector( Word-1 downto 0); |
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| 36 | |
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| 37 | type memory is |
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| 38 | array (natural range <>) of std_logic_vector(word-1 downto 0); |
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| 39 | |
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| 40 | type Core_io is |
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| 41 | record |
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| 42 | Instr_en :std_logic; -- active une instruction MPI |
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| 43 | Instr_ack :std_logic;-- signal la prise en compte de l'instruction |
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| 44 | Ready :std_logic;-- indique que la dernière fonction est terminée |
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| 45 | InitOk :std_logic; -- l'initialisation est terminée |
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| 46 | Hold_Req :std_logic;--Demande DMA |
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| 47 | Hold_Ack :std_logic;-- Autorisation DMA |
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| 48 | MemBusy :std_logic;-- active le refus de DMA (1 -> ignoré la requête DMA) |
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| 49 | RamSel :std_logic;-- indique le statut de la RAM (0 ->dispo 1->occupé par Core_MPI) |
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| 50 | IntState1 : natural range 0 to 255; --permet de stocker l'état des MAE interne dans les procédures |
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| 51 | IntState2 : natural range 0 to 255; |
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| 52 | Instruction :std_logic_vector (word-1 downto 0); |
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| 53 | WinId :natural range 0 to 255; --stocke le dernier Id utilisé par WinCreate |
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| 54 | IsMain : std_logic; -- indique si la librairie est principal |
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| 55 | Rank : natural range 0 to 16; --donne le rang du processus courant |
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| 56 | Spawned: std_logic; --indique que ce module a été activé par la bibliothèque |
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| 57 | end record; |
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| 58 | |
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| 59 | type typ_dpram is |
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| 60 | record |
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| 61 | |
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| 62 | |
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| 63 | clk_wr : STD_LOGIC; |
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| 64 | clk_rd : STD_LOGIC; |
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| 65 | we : STD_LOGIC; |
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| 66 | ena : STD_LOGIC; |
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| 67 | enb : STD_LOGIC; |
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| 68 | addr_wr: STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 69 | addr_rd : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 70 | data_in : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 71 | data_out : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 72 | |
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| 73 | |
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| 74 | end record; |
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| 75 | type Typ_MPIPort_in is |
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| 76 | record |
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| 77 | instruction : STD_LOGIC_VECTOR (Word -1 downto 0); |
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| 78 | instruction_en : STD_LOGIC; |
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| 79 | |
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| 80 | |
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| 81 | packet_ack : std_logic; |
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| 82 | ram_data_out : STD_LOGIC_VECTOR (Word-1 downto 0); |
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| 83 | |
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| 84 | hold_ack : STD_Logic; --autorisation par l'application |
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| 85 | clk : STD_LOGIC; |
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| 86 | reset : STD_LOGIC; |
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| 87 | |
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| 88 | end record; |
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| 89 | type Typ_MPIPort_out is |
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| 90 | record |
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| 91 | |
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| 92 | |
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| 93 | ram_we : STD_LOGIC; |
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| 94 | ram_en : STD_LOGIC; |
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| 95 | ram_data_in : STD_LOGIC_VECTOR (WORD-1 downto 0); |
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| 96 | ram_address_rd : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 97 | ram_address_wr : STD_LOGIC_VECTOR (ADRLEN-1 downto 0); |
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| 98 | packet_received : STD_LOGIC; |
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| 99 | barrier_completed : STD_LOGIC; |
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| 100 | instruction_fifo_full : STD_LOGIC; |
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| 101 | PushOut : STD_LOGIC_VECTOR (WORD-1 downto 0); |
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| 102 | |
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| 103 | hold_req : STD_Logic; --requete vers application |
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| 104 | end record; |
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| 105 | |
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| 106 | Type Ar_MPIPort_In is array (positive range <>) of Typ_MPIPort_in; |
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| 107 | Type Ar_MPIPort_out is array (positive range <>) of Typ_MPIPort_out; |
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| 108 | |
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| 109 | -- Declare constants |
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| 110 | |
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| 111 | -- constant <constant_name> : time := <time_unit> ns; |
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| 112 | -- constant <constant_name> : integer := <value>; |
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| 113 | -- |
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| 114 | -- Declare functions and procedure |
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| 115 | Component SWITCH_GEN is |
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| 116 | generic(number_of_ports : positive := 8); |
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| 117 | port( |
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| 118 | -- ports d'entree |
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| 119 | Port_in : in typ_portIO(1 to number_of_ports) ; |
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| 120 | -- |
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| 121 | |
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| 122 | -- port de sortie |
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| 123 | Port_out : out typ_portIO(1 to number_of_ports); |
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| 124 | -- |
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| 125 | -- signaux de controle |
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| 126 | cmd_in_en : in std_logic_vector(number_of_ports downto 1); |
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| 127 | data_in_en : in std_logic_vector(number_of_ports downto 1); |
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| 128 | data_out_en : in std_logic_vector(number_of_ports downto 1); |
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| 129 | fifo_in_full : out std_logic_vector(number_of_ports downto 1); |
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| 130 | fifo_in_empty : out std_logic_vector(number_of_ports downto 1); |
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| 131 | data_available : out std_logic_vector(number_of_ports downto 1); |
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| 132 | clk : in STD_LOGIC; |
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| 133 | reset : in STD_LOGIC); |
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| 134 | end component SWITCH_GEN; |
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| 135 | -- déclaration des fonctions utilisées |
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| 136 | |
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[22] | 137 | FUNCTION all_ones(s1:std_logic_vector) return std_logic; |
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[69] | 138 | --This function returns if the input vector has all ones and no zeros |
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[22] | 139 | FUNCTION all_zeros(s1:std_logic_vector) return std_logic; |
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[69] | 140 | --This function returns if the input vector has all zeros and no ones |
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[22] | 141 | FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; |
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| 142 | --This function increments an std_logic_vector type by '1', without |
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| 143 | --using any arithmatic |
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| 144 | |
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| 145 | FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector; |
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| 146 | --This function decrements an std_logic_vector type by '1', without |
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[69] | 147 | --using any arithmatic |
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| 148 | FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector; |
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| 149 | --renvoie un std_logic_vector de taille ADRLEN |
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| 150 | Function Stdlv (s1 : natural) return std_logic_vector; |
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| 151 | --renvoie un std_logic_vector de taille width |
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| 152 | Function Stdlv (s1 : natural;width:positive ) return std_logic_vector; |
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| 153 | function image(L: bit_vector) return String; |
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| 154 | function image(L: bit) return String; |
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| 155 | function image(L: std_logic_vector) return String; |
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| 156 | function image(L: std_logic) return String; |
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| 157 | -- function HexImage(L: unsigned) return String; |
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| 158 | -- function HexImage(L: signed) return String; |
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| 159 | -- function HexImage(L: std_ulogic_vector) return String; |
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| 160 | -- function HexImage(L: std_logic_vector) return String; |
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| 161 | -- function HexImage(L: bit_vector) return String; |
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| 162 | end CoreTypes; |
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| 163 | |
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| 164 | |
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| 165 | Package body CoreTypes is |
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| 166 | |
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| 167 | |
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[22] | 168 | FUNCTION incr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is |
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| 169 | --this function increments a std_logic_vector type by '1' |
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| 170 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 171 | VARIABLE tb : std_logic_vector(s1'high downto s1'low); |
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| 172 | BEGIN |
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| 173 | tb(s1'low) := en; |
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| 174 | V := s1; |
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| 175 | for i in (V'low + 1) to V'high loop |
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| 176 | tb(i) := V(i - 1) and tb(i -1); |
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| 177 | end loop; |
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| 178 | for i in V'low to V'high loop |
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| 179 | if(tb(i) = '1') then |
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| 180 | V(i) := not(V(i)); |
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| 181 | end if; |
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| 182 | end loop; |
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| 183 | return V; |
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| 184 | end incr_vec; -- end function |
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| 185 | |
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| 186 | FUNCTION dcr_vec(s1:std_logic_vector;en:std_logic) return std_logic_vector is |
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| 187 | --this function decrements a std_logic_vector type by '1' |
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| 188 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 189 | VARIABLE tb : std_logic_vector(s1'high downto s1'low); |
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| 190 | BEGIN |
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| 191 | tb(s1'low) := not(en); |
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| 192 | V := s1; |
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| 193 | for i in (V'low + 1) to V'high loop |
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| 194 | tb(i) := V(i - 1) or tb(i -1); |
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| 195 | end loop; |
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| 196 | for i in V'low to V'high loop |
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| 197 | if(tb(i) = '0') then |
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| 198 | V(i) := not(V(i)); |
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| 199 | end if; |
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| 200 | end loop; |
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| 201 | return V; |
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[69] | 202 | end dcr_vec; -- end function |
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[22] | 203 | FUNCTION all_ones(s1:std_logic_vector) return std_logic is |
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| 204 | --this function tells if all bits of a vector are '1' |
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| 205 | --return value Z is '1', then vector has all 1 bits |
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| 206 | --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 207 | VARIABLE Z : std_logic; |
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| 208 | BEGIN |
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| 209 | Z := s1(s1'low); |
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| 210 | FOR i IN (s1'low+1) to s1'high LOOP |
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| 211 | Z := Z AND s1(i); |
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| 212 | END LOOP; |
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| 213 | RETURN Z; |
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[69] | 214 | END all_ones; -- end function |
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[22] | 215 | FUNCTION all_zeros(s1:std_logic_vector) return std_logic is |
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| 216 | --this function tells if all bits of a vector are '0' |
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| 217 | --return value Z if '1', then vector has all 0 bits |
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| 218 | --VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 219 | VARIABLE Z : std_logic; |
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| 220 | BEGIN |
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| 221 | Z := '0'; |
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| 222 | FOR i IN (s1'low) to s1'high LOOP |
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| 223 | Z := Z OR s1(i); |
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| 224 | END LOOP; |
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| 225 | RETURN not(Z); |
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[69] | 226 | END all_zeros; -- end function |
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| 227 | |
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| 228 | FUNCTION Rol_Vec(s1:std_logic_vector) return std_logic_vector is |
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| 229 | --cette fonction fait roter un STD_logic d'un pas vers la gauche |
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[22] | 230 | VARIABLE V : std_logic_vector(s1'high downto s1'low) ; |
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| 231 | VARIABLE lb : std_logic :=s1(s1'left); |
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| 232 | BEGIN |
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| 233 | |
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| 234 | for i in V'left downto (V'right+1) loop |
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| 235 | V(i) := s1(i - 1) ; |
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| 236 | end loop; |
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| 237 | V(V'right):=lb; |
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| 238 | return V; |
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[69] | 239 | end Rol_vec; |
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| 240 | Function Stdlv (s1 : natural ) return std_logic_vector is |
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| 241 | VARIABLE V : std_logic_vector(ADRLEN-1 downto 0); |
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| 242 | begin |
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| 243 | V:=std_logic_vector(to_unsigned(s1,ADRLEN)); |
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| 244 | return V; |
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| 245 | end stdlv; |
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| 246 | Function Stdlv (s1 : natural;width:positive ) return std_logic_vector is |
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| 247 | VARIABLE V : std_logic_vector(width-1 downto 0); |
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| 248 | begin |
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| 249 | V:=std_logic_vector(to_unsigned(s1,width)); |
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| 250 | return V; |
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| 251 | end stdlv; |
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| 252 | |
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[40] | 253 | -- Start of heximage functions |
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| 254 | --function HexImage(L: bit_vector) return String is |
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| 255 | --begin |
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| 256 | --return(HexImage(imge(L))); |
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| 257 | --end function HexImage; |
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| 258 | -- |
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| 259 | --function HexImage(L: std_ulogic_vector) return String is |
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| 260 | --begin |
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| 261 | --return(HexImage(image(to_x01(L)))); |
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| 262 | --end function HexImage; |
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| 263 | |
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| 264 | --function HexImage(L: std_logic_vector) return String is |
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| 265 | --begin |
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| 266 | --return(HexImage(imge(to_x01(L)))); |
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| 267 | --end function HexImage; |
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| 268 | -- |
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| 269 | --function HexImage(L: signed) return String is |
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| 270 | --begin |
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| 271 | --return(HexImage(imge(L))); |
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| 272 | --end function HexImage; |
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| 273 | -- |
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| 274 | --function HexImage(L: unsigned) return String is |
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| 275 | --begin |
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| 276 | --return(HexImage(image(L))); |
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| 277 | --end function HexImage; |
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| 278 | -- End of heximage functions |
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| 279 | -- Start of an example image function |
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| 280 | function image(L: bit) return String is |
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[42] | 281 | variable bit_image: String(1 to 1) := bit'image(L); |
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[40] | 282 | begin |
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[42] | 283 | return(bit_image(1 to 1)); |
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[40] | 284 | end function image; |
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[69] | 285 | |
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| 286 | |
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[40] | 287 | function image(L: std_logic) return String is |
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[69] | 288 | variable bit_image: String(1 to 3) := std_logic'image(L); |
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[40] | 289 | begin |
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[42] | 290 | return(bit_image(1 to 1)); |
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[40] | 291 | end function image; |
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[69] | 292 | |
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[40] | 293 | function image(L: bit_vector) return String is |
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| 294 | variable Lx: bit_vector(1 to L'length); |
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| 295 | variable RetVal: String(1 to L'length); |
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| 296 | begin |
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| 297 | Lx := L; |
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| 298 | for i in Lx'range loop |
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| 299 | RetVal(i to i) := image(Lx(i)); |
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| 300 | end loop; |
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| 301 | return(RetVal); |
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[69] | 302 | end function image; |
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| 303 | |
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| 304 | |
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[40] | 305 | function image(L: std_logic_vector) return String is |
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| 306 | variable Lx: std_logic_vector(1 to L'length); |
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| 307 | variable RetVal: String(1 to L'length); |
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| 308 | begin |
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| 309 | Lx := L; |
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| 310 | for i in Lx'range loop |
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| 311 | RetVal(i to i) := image(Lx(i)); |
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| 312 | end loop; |
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| 313 | return(RetVal); |
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[69] | 314 | end function image; |
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| 315 | end CoreTypes; |
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