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source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/OUTPUT_PORT_MODULE.vhd @ 69

Last change on this file since 69 was 69, checked in by rolagamo, 11 years ago

File size: 5.8 KB

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2	----------------------------------------------------------------------------------
3	-- Company:
4	-- Engineer:
5	--
6	-- Create Date: 09:29:48 04/18/2011
7	-- Design Name:
8	-- Module Name: OUTPUT_PORT_MODULE - Behavioral_description
9	-- Project Name:
10	-- Target Devices:
11	-- Tool versions:
12	-- Description:
13	-- cette version du module de sortie se limite à une instance du fifo ordinaire
14	-- les données son emise en sortie à chaque cycle d'horloge
15	-- Dependencies:
16	--
17	-- Revision: 07-08-2013
18	-- Revision 0.01 - File Created
19	-- Additional Comments: Ajout d'un délai pour ignorer les paquets qui sont là depuis
20	-- longtemps
21	--
22	----------------------------------------------------------------------------------
23	library IEEE;
24	use IEEE.STD_LOGIC_1164.ALL;
25	--use IEEE.STD_LOGIC_ARITH.ALL;
26	--use IEEE.STD_LOGIC_UNSIGNED.ALL;
27	USE ieee.numeric_std.ALL;
28	Library NocLib;
29	use NocLib.CoreTypes.all;
30	---- Uncomment the following library declaration if instantiating
31	---- any Xilinx primitives in this code.
32	--library UNISIM;
33	--use UNISIM.VComponents.all;
34
35	entity OUTPUT_PORT_MODULE is
36	Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0);
37	reset : in STD_LOGIC;
38	clk : in STD_LOGIC;
39	wr_en : in STD_LOGIC;
40	data_out : out STD_LOGIC_VECTOR (Word-1 downto 0);
41	fifo_full : out std_logic;
42	data_avalaible : out std_logic;
43	rd_out_en : in STD_LOGIC);
44	end OUTPUT_PORT_MODULE;
45
46	architecture Behavioral_description of OUTPUT_PORT_MODULE is
47	-- declaration du FIFO 64 octets
48	component FIFO_256_FWFT
49	port (
50	clk: IN std_logic;
51	din: IN std_logic_VECTOR(Word-1 downto 0);
52	rd_en: IN std_logic;
53	srst: IN std_logic;
54	wr_en: IN std_logic;
55	dout: out std_logic_VECTOR(Word-1 downto 0);
56	empty: OUT std_logic;
57	full: OUT std_logic);
58	end component;
59	--definition du type etat pour les fsm
60	type typ_outfsm is (Idle,waiting,dropping,reading);
61	type typ_receiv is (r_wait,r_head,r_len,r_glen,r_data,r_pulse,r_end);
62
63	signal EtRec : typ_receiv;
64	signal Et_out_fsm : typ_outfsm;
65	signal fifo_empty : std_logic;
66	signal sw : std_logic:='0'; -- permet de positionner le mux sur les signaux internes
67	signal tlimit : natural:=0; --permet de compter les impulsions de temps
68	signal n : natural:=0; --utiliser pour la mae du tampon de sortie
69	signal rcv_start : std_logic; --début de la réception
70	signal rcv_ack : std_logic; -- acquittement de la réception
71	signal rcv_comp : std_logic; -- fin de la réception
72	signal spop,pop,rd_en,dat_avail : std_logic:='0';
73	signal mem,fifo_out : std_logic_vector(Word-1 downto 0); --variable tampon sans intérêt réel
74	begin
75	-- instantiation du FIFO_64
76	OUTPUT_PORT_FIFO : FIFO_256_FWFT
77	port map (
78	clk => clk,
79	din => data_in,
80	rd_en => rd_en,
81	srst => reset,
82	wr_en => wr_en,
83	dout => fifo_out,
84	empty => fifo_empty,
85	full => fifo_full);
86
87
88	outport_proc : process(clk,reset,fifo_empty)
89	begin
90	if rising_edge(clk) then
91	if reset='1' then
92	n<=0;
93	Et_out_fsm<=Idle;
94	else
95	case(Et_out_fsm) is
96
97	when Idle => --idle
98	if fifo_empty = '0' then
99	Et_Out_fsm<=waiting;
100	end if;
101	tlimit<=0;
102	sw<='0';
103	when reading =>
104	if rd_out_en='0' then
105	Et_out_fsm<=Idle;
106	end if;
107	sw<='0';
108	when waiting => --counting
109	if rd_out_en='1' then
110	Et_out_fsm<=reading;
111	elsif tlimit=350 then
112	Et_out_fsm<=dropping;
113	tlimit<=0;
114	else
115	tlimit<=tlimit+1;
116	end if;
117	sw<='0';
118	when dropping => --dropping packet
119	if n=0 then
120	rcv_start<='1';
121	n<=1;
122	sw<='1';
123	elsif n=1 then
124	if rcv_comp='1' then
125	rcv_ack<='1';
126	rcv_start<='0';
127	n<=2;
128	end if;
129	sw<='1';
130	elsif n=2 then
131	sw<='0';
132	Et_out_fsm<=Idle;
133	n<=0;
134	end if;
135
136	end case;
137	end if;
138	end if;
139	end process outport_proc;
140	data_out<=fifo_out;
141	mux_proc : process (sw,rd_out_en,pop,fifo_empty)
142	begin
143	if sw='1' then --mode drop
144	rd_en<=pop;
145	data_avalaible <='0'; --plus de données dans le tampon !
146	else
147	rd_en<=rd_out_en;
148	data_avalaible <= not fifo_empty;
149	end if;
150	end process mux_proc;
151	proc_receiv : process (clk,reset)
152	variable dlen,i: natural range 0 to 255 :=0;
153
154	begin
155	if reset='1' then
156	etrec<=r_wait;
157
158	else
159	if rising_edge(clk) then -- le process s'exécute sur chaque front
160	-- montant de l'horloge
161	case etrec is
162	when r_wait =>
163
164	i:=0;
165	if fifo_empty='0' and rcv_start='1' then
166
167	etrec<=r_head;
168	mem<=fifo_out;
169
170	end if;
171	when r_head =>
172	mem<=fifo_out; --l'en-tête
173
174	etrec<=r_len;
175	when r_len =>
176	dlen:=to_integer(unsigned(fifo_out));
177	mem<=fifo_out; -- la longueur
178
179	if dlen>2 then
180	etrec<=r_data;
181	else
182	etrec<=r_end;
183	end if;
184	i:=1;
185
186	when r_data =>
187	if fifo_empty='0' then
188	if i<dlen-2 then
189	i:=i+1;
190	mem<=fifo_out;
191
192
193	else
194	etrec<=r_pulse;
195
196	mem<=fifo_out;
197	end if;
198	-- time out à prévoir ici
199	end if;
200	when r_pulse =>
201	etrec<=r_end;
202
203	when r_end =>
204	if rcv_ack='1' then
205	etrec<=r_wait;
206	end if;
207
208	when others =>
209
210
211	etrec<=r_wait;
212	end case;
213	end if;
214	end if;
215	end process;
216
217	pop<=spop;
218
219	rec_value : process (etrec)
220	begin
221	case etrec is
222	when r_wait =>
223	spop<='0';
224	rcv_comp<='0';
225	when r_head =>
226
227	spop<='1';
228	rcv_comp<='0';
229
230	when r_len =>
231	spop<='1';
232	when r_data =>
233	spop<='1';
234	when r_pulse =>
235	spop<='0';
236	rcv_comp<='1';
237	when r_end =>
238	spop<='0';
239	rcv_comp<='1';
240	when others =>
241	spop<='0';
242	rcv_comp<='0';
243	end case;
244	end process;
245
246	end Behavioral_description;
247

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