source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SCHEDULER2_2.VHD

Last change on this file was 22, checked in by rolagamo, 12 years ago
File size: 5.4 KB
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1---------------------------------------------------------------------------------
2-- Company:
3-- Engineer: KIEGAING EMMANUEL GEL EN 5
4--
5-- Create Date:    03:56:34 05/06/2011
6-- Design Name:
7-- Module Name:    Sheduler - Behavioral
8-- Project Name:
9-- Target Devices:
10-- Tool versions:
11-- Description: Module de l'ordonnanceur du switch crossbar
12-- l'algorithme utilisée est le DPA (diagonal propagation arbiter)
13--
14-- Dependencies:
15--
16-- Revision:
17-- Revision 0.01 - File Created
18-- Additional Comments:
19--
20----------------------------------------------------------------------------------
21library IEEE;
22use IEEE.STD_LOGIC_1164.ALL;
23use IEEE.STD_LOGIC_ARITH.ALL;
24use IEEE.STD_LOGIC_UNSIGNED.ALL;
25--use Work.Sheduler_package.all;
26
27---- Uncomment the following library declaration if instantiating
28---- any Xilinx primitives in this code.
29--library UNISIM;
30--use UNISIM.VComponents.all;
31entity Scheduler2_2 is
32    Port ( Request : in  STD_LOGIC_VECTOR (4 downto 1);
33                   Fifo_full : in STD_LOGIC_VECTOR (2 downto 1);
34           clk : in  STD_LOGIC;
35           reset : in  STD_LOGIC;
36            priority_rotation : in  STD_LOGIC_VECTOR (2 downto 1);
37           port_grant : out  STD_LOGIC_VECTOR (4 downto 1));
38end Scheduler2_2;
39
40architecture Behavioral of Scheduler2_2 is
41--Declaration du types
42--tableau de signaux de connexion des cellules arbitres
43TYPE C_Bar_Signal_Array IS ARRAY(3 downto 1) of STD_LOGIC_VECTOR(2 downto 1);
44-- declaration du composant cellule d'arbitrage
45Component Arbiter
46  PORT (P, Fifo_full,Request, West,North : in  STD_LOGIC;
47        Grant,East,South : out  STD_LOGIC );
48End Component;--Signaux de connexion des cellues
49SIGNAL south_2_north :  C_Bar_Signal_Array; -- connexion south north
50SIGNAL east_2_west   :  C_Bar_Signal_Array; -- connexion east west
51SIGNAL Signal_mask      : C_Bar_Signal_Array;-- connexion des masques de priorité
52SIGNAL Signal_grant     : C_Bar_Signal_Array;-- connexion des signaux de validation
53SIGNAL Signal_priority  : STD_LOGIC_VECTOR (3 DOWNTO 1);--signal pour la connection des vecteur de priorité
54SIGNAL High         : std_logic;--niveau pour les cellules des extremités nord et ouest
55 signal grant_latch : std_logic_vector(4 downto 1);
56 signal priority_rotation_en : std_logic;
57 signal Grant ,req_grant :  std_logic_vector(4 downto 1);
58 begin
59
60--validation de la rotation de priorité lorsque aucun port n'emet
61 req_grant<=(request and grant_latch);
62 priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 3 else       '0';
63--latch servant qui memorise le signal grant pendant a transmission
64grant_latch_process : process(clk)
65 begin
66  if rising_edge(clk) then
67   if reset = '1' then
68                grant_latch <= (others => '0');
69         elsif priority_rotation_en = '1' then
70           grant_latch <= Grant;
71   end if;
72   end if;
73 end process;
74 port_grant <= grant_latch;
75 Grant(1)  <= Signal_grant(1)(1) or Signal_grant(3)(1); --  Grant(1,1)
76Grant(2)  <= Signal_grant(2)(2) ;                      --  Grant(1,2)
77Grant(3)  <= Signal_grant(2)(1) ;                      --  Grant(2,1)
78Grant(4)  <= Signal_grant(1)(2) or Signal_grant(3)(2); --  Grant(2,2)
79High <= '1';
80
81----instantiations des cellules arbitres et interconnection
82
83-------------------------- Diagonale n° 1
84
85
86Arbiter_1_1 : Arbiter
87
88PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(1), 
89South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1));
90
91Arbiter_1_2 : Arbiter
92
93PORT MAP (Request => Request(4), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(2), 
94South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2));
95
96-------------------------- Diagonale n° 2
97
98
99Arbiter_2_1 : Arbiter
100
101PORT MAP (Request => Request(3), North => south_2_north(1)(1), West => east_2_west(1)(2), P => Signal_priority(2), Fifo_full => Fifo_full(1), 
102South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1));
103
104Arbiter_2_2 : Arbiter
105
106PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), 
107South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2));
108
109-------------------------- Diagonale n° 3
110
111
112Arbiter_3_1 : Arbiter
113
114PORT MAP (Request => Request(1), North => south_2_north(2)(1), West => east_2_west(2)(2), P => Signal_priority(1), Fifo_full => Fifo_full(1), 
115South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1));
116
117Arbiter_3_2 : Arbiter
118
119PORT MAP (Request => Request(4), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), 
120South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2));
121
122
123--processus permettant de roter la priorité des diagonales à chaque front d'horloge
124 -- rotation round robin
125         round_robin : process(clk)
126        begin
127                if rising_edge(clk) then
128                 if reset ='1' then
129                    Signal_priority <= "110";
130                  elsif priority_rotation_en = '1' then
131                    case Signal_priority is
132                       when "110" => Signal_priority <= "011";
133                       when "011" => Signal_priority <= "110";
134                       when others    => Signal_priority <= "110";
135                  end case;
136                 end if;
137             end if;
138         end process;
139
140end Behavioral;
141
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