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SWITCH_GENERIQUE.vhd @ 69

Last change on this file since 69 was 22, checked in by rolagamo, 12 years ago

File size: 255.6 KB

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1	----------------------------------------------------------------------------------
2	-- Company: ENSET 2011
3	-- Engineer: GAMOM NGOUNOU ET KIEGAING EMMANUEL ET TAGNE FRANKLIN EN 5
4	--
5	-- Create Date: 03:40:47 06/18/2011
6	-- Design Name:
7	-- Module Name: SWITCH_GENERIQUE - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	-- fichier principal du switch générique; en fonction du parametre generique le
13	-- les directive de generation conditionnelle permettent de ne générer et synthétiser uniquement la logique
14	-- nécessaire à l'implémentation du switch de la dimension voulue
15	-- Dependencies:
16	--
17	-- Revision:
18	-- Revision 0.01 - File Created
19	-- Additional Comments:
20	--
21	----------------------------------------------------------------------------------
22	library IEEE;
23	use IEEE.STD_LOGIC_1164.ALL;
24	use IEEE.STD_LOGIC_ARITH.ALL;
25	use IEEE.STD_LOGIC_UNSIGNED.ALL;
26
27	---- Uncomment the following library declaration if instantiating
28	---- any Xilinx primitives in this code.
29	--library UNISIM;
30	--use UNISIM.VComponents.all;
31
32	entity SWITCH_GENERIQUE is
33	generic(number_of_ports : positive := 8);
34	port(
35	-- ports d'entree
36	Port1_in : in STD_LOGIC_VECTOR (7 downto 0);
37	Port2_in : in STD_LOGIC_VECTOR (7 downto 0);
38	Port3_in : in STD_LOGIC_VECTOR (7 downto 0);
39	Port4_in : in STD_LOGIC_VECTOR (7 downto 0);
40	Port5_in : in STD_LOGIC_VECTOR (7 downto 0);
41	Port6_in : in STD_LOGIC_VECTOR (7 downto 0);
42	Port7_in : in STD_LOGIC_VECTOR (7 downto 0);
43	Port8_in : in STD_LOGIC_VECTOR (7 downto 0);
44	Port9_in : in STD_LOGIC_VECTOR (7 downto 0);
45	Port10_in : in STD_LOGIC_VECTOR (7 downto 0);
46	Port11_in : in STD_LOGIC_VECTOR (7 downto 0);
47	Port12_in : in STD_LOGIC_VECTOR (7 downto 0);
48	Port13_in : in STD_LOGIC_VECTOR (7 downto 0);
49	Port14_in : in STD_LOGIC_VECTOR (7 downto 0);
50	Port15_in : in STD_LOGIC_VECTOR (7 downto 0);
51	Port16_in : in STD_LOGIC_VECTOR (7 downto 0);
52
53	-- port de sortie
54	Port1_out : out STD_LOGIC_VECTOR (7 downto 0);
55	Port2_out : out STD_LOGIC_VECTOR (7 downto 0);
56	Port3_out : out STD_LOGIC_VECTOR (7 downto 0);
57	Port4_out : out STD_LOGIC_VECTOR (7 downto 0);
58	Port5_out : out STD_LOGIC_VECTOR (7 downto 0);
59	Port6_out : out STD_LOGIC_VECTOR (7 downto 0);
60	Port7_out : out STD_LOGIC_VECTOR (7 downto 0);
61	Port8_out : out STD_LOGIC_VECTOR (7 downto 0);
62	Port9_out : out STD_LOGIC_VECTOR (7 downto 0);
63	Port10_out : out STD_LOGIC_VECTOR (7 downto 0);
64	Port11_out : out STD_LOGIC_VECTOR (7 downto 0);
65	Port12_out : out STD_LOGIC_VECTOR (7 downto 0);
66	Port13_out : out STD_LOGIC_VECTOR (7 downto 0);
67	Port14_out : out STD_LOGIC_VECTOR (7 downto 0);
68	Port15_out : out STD_LOGIC_VECTOR (7 downto 0);
69	Port16_out : out STD_LOGIC_VECTOR (7 downto 0);
70	-- signaux de controle
71	data_in_en : in std_logic_vector(number_of_ports downto 1);
72	data_out_en : in std_logic_vector(number_of_ports downto 1);
73	fifo_in_full : out std_logic_vector(number_of_ports downto 1);
74	fifo_in_empty : out std_logic_vector(number_of_ports downto 1);
75	data_available : out std_logic_vector(number_of_ports downto 1);
76	clk : in STD_LOGIC;
77	reset : in STD_LOGIC);
78	end SWITCH_GENERIQUE;
79
80	architecture Behavioral of SWITCH_GENERIQUE is
81	-- declaration des modules du switch generique
82	-- le module de gestion des ports d'entrée
83
84	COMPONENT INPUT_PORT_MODULE
85	generic(number_of_ports : positive := 4);
86	Port ( data_in : in STD_LOGIC_VECTOR (7 downto 0);
87	data_in_en : in STD_LOGIC;
88	reset : in STD_LOGIC;
89	clk : in STD_LOGIC;
90	request : out STD_LOGIC_VECTOR (number_of_ports downto 1);
91	grant : in STD_LOGIC_VECTOR (number_of_ports downto 1);
92	fifo_full : out STD_LOGIC;
93	fifo_empty : out STD_LOGIC;
94	priority_rotation : out std_logic;
95	data_out : out STD_LOGIC_VECTOR (7 downto 0);
96	data_out_pulse : out std_logic);
97	END COMPONENT;
98
99	-- le module des ports de sortie
100
101	COMPONENT OUTPUT_PORT_MODULE
102	PORT(
103	data_in : IN std_logic_vector(7 downto 0);
104	reset : IN std_logic;
105	clk : IN std_logic;
106	wr_en : IN std_logic;
107	rd_out_en : IN std_logic;
108	data_out : OUT std_logic_vector(7 downto 0);
109	fifo_full : OUT std_logic;
110	data_avalaible : OUT std_logic
111	);
112	END COMPONENT;
113
114	-- le module du crossbar
115	COMPONENT Crossbar
116	generic
117	(
118	number_of_crossbar_ports: positive := 4
119	);
120	Port ( Port1_in : in STD_LOGIC_VECTOR (7 downto 0);
121	Port2_in : in STD_LOGIC_VECTOR (7 downto 0);
122	Port3_in : in STD_LOGIC_VECTOR (7 downto 0);
123	Port4_in : in STD_LOGIC_VECTOR (7 downto 0);
124	Port5_in : in STD_LOGIC_VECTOR (7 downto 0);
125	Port6_in : in STD_LOGIC_VECTOR (7 downto 0);
126	Port7_in : in STD_LOGIC_VECTOR (7 downto 0);
127	Port8_in : in STD_LOGIC_VECTOR (7 downto 0);
128	Port9_in : in STD_LOGIC_VECTOR (7 downto 0);
129	Port10_in : in STD_LOGIC_VECTOR (7 downto 0);
130	Port11_in : in STD_LOGIC_VECTOR (7 downto 0);
131	Port12_in : in STD_LOGIC_VECTOR (7 downto 0);
132	Port13_in : in STD_LOGIC_VECTOR (7 downto 0);
133	Port14_in : in STD_LOGIC_VECTOR (7 downto 0);
134	Port15_in : in STD_LOGIC_VECTOR (7 downto 0);
135	Port16_in : in STD_LOGIC_VECTOR (7 downto 0);
136
137	Port1_pulse_in : in std_logic;
138	Port2_pulse_in : in std_logic;
139	Port3_pulse_in : in std_logic;
140	Port4_pulse_in : in std_logic;
141	Port5_pulse_in : in std_logic;
142	Port6_pulse_in : in std_logic;
143	Port7_pulse_in : in std_logic;
144	Port8_pulse_in : in std_logic;
145	Port9_pulse_in : in std_logic;
146	Port10_pulse_in : in std_logic;
147	Port11_pulse_in : in std_logic;
148	Port12_pulse_in : in std_logic;
149	Port13_pulse_in : in std_logic;
150	Port14_pulse_in : in std_logic;
151	Port15_pulse_in : in std_logic;
152	Port16_pulse_in : in std_logic;
153
154	Port1_pulse_out : out std_logic;
155	Port2_pulse_out : out std_logic;
156	Port3_pulse_out : out std_logic;
157	Port4_pulse_out : out std_logic;
158	Port5_pulse_out : out std_logic;
159	Port6_pulse_out : out std_logic;
160	Port7_pulse_out : out std_logic;
161	Port8_pulse_out : out std_logic;
162	Port9_pulse_out : out std_logic;
163	Port10_pulse_out : out std_logic;
164	Port11_pulse_out : out std_logic;
165	Port12_pulse_out : out std_logic;
166	Port13_pulse_out : out std_logic;
167	Port14_pulse_out : out std_logic;
168	Port15_pulse_out : out std_logic;
169	Port16_pulse_out : out std_logic;
170
171	Port1_out : out STD_LOGIC_VECTOR (7 downto 0);
172	Port2_out : out STD_LOGIC_VECTOR (7 downto 0);
173	Port3_out : out STD_LOGIC_VECTOR (7 downto 0);
174	Port4_out : out STD_LOGIC_VECTOR (7 downto 0);
175	Port5_out : out STD_LOGIC_VECTOR (7 downto 0);
176	Port6_out : out STD_LOGIC_VECTOR (7 downto 0);
177	Port7_out : out STD_LOGIC_VECTOR (7 downto 0);
178	Port8_out : out STD_LOGIC_VECTOR (7 downto 0);
179	Port9_out : out STD_LOGIC_VECTOR (7 downto 0);
180	Port10_out : out STD_LOGIC_VECTOR (7 downto 0);
181	Port11_out : out STD_LOGIC_VECTOR (7 downto 0);
182	Port12_out : out STD_LOGIC_VECTOR (7 downto 0);
183	Port13_out : out STD_LOGIC_VECTOR (7 downto 0);
184	Port14_out : out STD_LOGIC_VECTOR (7 downto 0);
185	Port15_out : out STD_LOGIC_VECTOR (7 downto 0);
186	Port16_out : out STD_LOGIC_VECTOR (7 downto 0);
187
188	Ctrl : in STD_LOGIC_VECTOR (number_of_crossbar_ports*number_of_crossbar_ports downto 1)
189	);
190	END COMPONENT;
191
192	-- déclaration du scheduler
193	COMPONENT Scheduler
194	generic(number_of_ports : positive := 4);
195	Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1);
196	Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1);
197	clk : in STD_LOGIC;
198	reset : in STD_LOGIC;
199	priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1);
200	port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1));
201	END COMPONENT;
202
203	--declaration des signaux de connection entre les modules du switch
204	--type port_connection_type is array(16 downto 1) of std_logic_vector(7 downto 1);
205	--signal crossbar_port_in_connetion : port_connection_type;
206	--signal crossbar_port_out_connetion :port_connection_type;
207	--signal request_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
208	--signal grant_connection : std_logic_vector(number_of_ports*number_of_ports downto 1);
209	--signal priority_rotation_connection : std_logic_vector(number_of_ports downto 1);
210	--signal fifo_out_full_connection : std_logic_vector(1 to number_of_ports);
211	--signal crossbar_in_pulse_connection : std_logic_vector(number_of_ports downto 1);
212	--signal crossbar_out_pulse_connection : std_logic_vector(number_of_ports downto 1);
213
214	Signal Request_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
215	Signal grant_signal : STD_LOGIC_VECTOR(number_of_ports*number_of_ports downto 1);
216	Signal priority_rotation_signal : STD_LOGIC_VECTOR(number_of_ports downto 1);
217	signal fifo_out_full_signal : std_logic_vector(number_of_ports downto 1);
218	signal crossbar_in_port1 : std_logic_vector(7 downto 0);
219	signal crossbar_in_port2 : std_logic_vector(7 downto 0);
220	signal crossbar_in_port3 : std_logic_vector(7 downto 0);
221	signal crossbar_in_port4 : std_logic_vector(7 downto 0);
222	signal crossbar_in_port5 : std_logic_vector(7 downto 0);
223	signal crossbar_in_port6 : std_logic_vector(7 downto 0);
224	signal crossbar_in_port7 : std_logic_vector(7 downto 0);
225	signal crossbar_in_port8 : std_logic_vector(7 downto 0);
226	signal crossbar_in_port9 : std_logic_vector(7 downto 0);
227	signal crossbar_in_port10 : std_logic_vector(7 downto 0);
228	signal crossbar_in_port11 : std_logic_vector(7 downto 0);
229	signal crossbar_in_port12 : std_logic_vector(7 downto 0);
230	signal crossbar_in_port13 : std_logic_vector(7 downto 0);
231	signal crossbar_in_port14 : std_logic_vector(7 downto 0);
232	signal crossbar_in_port15 : std_logic_vector(7 downto 0);
233	signal crossbar_in_port16: std_logic_vector(7 downto 0);
234
235	signal crossbar_out_port1 : std_logic_vector(7 downto 0);
236	signal crossbar_out_port2 : std_logic_vector(7 downto 0);
237	signal crossbar_out_port3 : std_logic_vector(7 downto 0);
238	signal crossbar_out_port4 : std_logic_vector(7 downto 0);
239	signal crossbar_out_port5 : std_logic_vector(7 downto 0);
240	signal crossbar_out_port6 : std_logic_vector(7 downto 0);
241	signal crossbar_out_port7 : std_logic_vector(7 downto 0);
242	signal crossbar_out_port8 : std_logic_vector(7 downto 0);
243	signal crossbar_out_port9 : std_logic_vector(7 downto 0);
244	signal crossbar_out_port10 : std_logic_vector(7 downto 0);
245	signal crossbar_out_port11 : std_logic_vector(7 downto 0);
246	signal crossbar_out_port12 : std_logic_vector(7 downto 0);
247	signal crossbar_out_port13 : std_logic_vector(7 downto 0);
248	signal crossbar_out_port14 : std_logic_vector(7 downto 0);
249	signal crossbar_out_port15 : std_logic_vector(7 downto 0);
250	signal crossbar_out_port16 : std_logic_vector(7 downto 0);
251
252	signal crossbar_in_pulse1 : std_logic;
253	signal crossbar_in_pulse2 : std_logic;
254	signal crossbar_in_pulse3 : std_logic;
255	signal crossbar_in_pulse4 : std_logic;
256	signal crossbar_in_pulse5 : std_logic;
257	signal crossbar_in_pulse6 : std_logic;
258	signal crossbar_in_pulse7 : std_logic;
259	signal crossbar_in_pulse8 : std_logic;
260	signal crossbar_in_pulse9 : std_logic;
261	signal crossbar_in_pulse10 : std_logic;
262	signal crossbar_in_pulse11 : std_logic;
263	signal crossbar_in_pulse12 : std_logic;
264	signal crossbar_in_pulse13 : std_logic;
265	signal crossbar_in_pulse14 : std_logic;
266	signal crossbar_in_pulse15 : std_logic;
267	signal crossbar_in_pulse16 : std_logic;
268
269
270	signal crossbar_out_pulse1 : std_logic;
271	signal crossbar_out_pulse2 : std_logic;
272	signal crossbar_out_pulse3 : std_logic;
273	signal crossbar_out_pulse4 : std_logic;
274	signal crossbar_out_pulse5 : std_logic;
275	signal crossbar_out_pulse6 : std_logic;
276	signal crossbar_out_pulse7 : std_logic;
277	signal crossbar_out_pulse8 : std_logic;
278	signal crossbar_out_pulse9 : std_logic;
279	signal crossbar_out_pulse10 : std_logic;
280	signal crossbar_out_pulse11 : std_logic;
281	signal crossbar_out_pulse12 : std_logic;
282	signal crossbar_out_pulse13 : std_logic;
283	signal crossbar_out_pulse14 : std_logic;
284	signal crossbar_out_pulse15 : std_logic;
285	signal crossbar_out_pulse16 : std_logic;
286
287
288	begin
289	-- intstanciation et connexion des modules du switch en fonction du nombre de ports
290	-- le circuit genere depend du parametre generique nombre de ports
291	-- switch 2 ports
292	switch2x2 : if number_of_ports = 2 generate
293
294	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
295	GENERIC MAP(number_of_ports =>2)
296	PORT MAP(
297	data_in => Port1_in,
298	data_in_en => data_in_en(1),
299	reset => reset,
300	clk =>clk,
301	grant(1) => grant_signal(1),
302	grant(2) => grant_signal(2),
303	fifo_full =>fifo_in_full(1),
304	priority_rotation => priority_rotation_signal(1),
305	fifo_empty => fifo_in_empty(1),
306	data_out =>crossbar_in_port1,
307	data_out_pulse =>crossbar_in_pulse1,
308	request(1) =>request_signal(1),
309	request(2) =>request_signal(2)
310	);
311
312	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
313	GENERIC MAP(number_of_ports =>2)
314	PORT MAP(
315	data_in => Port2_in,
316	data_in_en => data_in_en(2),
317	reset => reset,
318	clk =>clk,
319	grant(3) => grant_signal(3),
320	grant(4) => grant_signal(4),
321	fifo_full =>fifo_in_full(2),
322	priority_rotation => priority_rotation_signal(2),
323	fifo_empty => fifo_in_empty(2),
324	data_out =>crossbar_in_port2,
325	data_out_pulse =>crossbar_in_pulse2,
326	request(3) =>request_signal(3),
327	request(4) =>request_signal(4)
328	);
329
330	end generate switch2x2;
331
332
333	-- switch 3 ports
334	switch3x3 : if number_of_ports = 3 generate
335
336	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
337	GENERIC MAP(number_of_ports =>3)
338	PORT MAP(
339	data_in => Port1_in,
340	data_in_en => data_in_en(1),
341	reset => reset,
342	clk =>clk,
343	grant(1) => grant_signal(1),
344	grant(2) => grant_signal(2),
345	grant(3) => grant_signal(3),
346	fifo_full =>fifo_in_full(1),
347	priority_rotation => priority_rotation_signal(1),
348	fifo_empty => fifo_in_empty(1),
349	data_out =>crossbar_in_port1,
350	data_out_pulse =>crossbar_in_pulse1,
351	request(1) =>request_signal(1),
352	request(2) =>request_signal(2),
353	request(3) =>request_signal(3)
354	);
355
356	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
357	GENERIC MAP(number_of_ports =>3)
358	PORT MAP(
359	data_in => Port2_in,
360	data_in_en => data_in_en(2),
361	reset => reset,
362	clk =>clk,
363	grant(4) => grant_signal(4),
364	grant(5) => grant_signal(5),
365	grant(6) => grant_signal(6),
366	fifo_full =>fifo_in_full(2),
367	priority_rotation => priority_rotation_signal(2),
368	fifo_empty => fifo_in_empty(2),
369	data_out =>crossbar_in_port2,
370	data_out_pulse =>crossbar_in_pulse2,
371	request(4) =>request_signal(4),
372	request(5) =>request_signal(5),
373	request(6) =>request_signal(6)
374	);
375
376	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
377	GENERIC MAP(number_of_ports =>3)
378	PORT MAP(
379	data_in => Port3_in,
380	data_in_en => data_in_en(3),
381	reset => reset,
382	clk =>clk,
383	grant(7) => grant_signal(7),
384	grant(8) => grant_signal(8),
385	grant(9) => grant_signal(9),
386	fifo_full =>fifo_in_full(3),
387	priority_rotation => priority_rotation_signal(3),
388	fifo_empty => fifo_in_empty(3),
389	data_out =>crossbar_in_port3,
390	data_out_pulse =>crossbar_in_pulse3,
391	request(7) =>request_signal(7),
392	request(8) =>request_signal(8),
393	request(9) =>request_signal(9)
394	);
395
396	end generate switch3x3;
397
398
399	-- switch 4 ports
400	switch4x4 : if number_of_ports = 4 generate
401
402	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
403	GENERIC MAP(number_of_ports =>4)
404	PORT MAP(
405	data_in => Port1_in,
406	data_in_en => data_in_en(1),
407	reset => reset,
408	clk =>clk,
409	grant(1) => grant_signal(1),
410	grant(2) => grant_signal(2),
411	grant(3) => grant_signal(3),
412	grant(4) => grant_signal(4),
413	fifo_full =>fifo_in_full(1),
414	priority_rotation => priority_rotation_signal(1),
415	fifo_empty => fifo_in_empty(1),
416	data_out =>crossbar_in_port1,
417	data_out_pulse =>crossbar_in_pulse1,
418	request(1) =>request_signal(1),
419	request(2) =>request_signal(2),
420	request(3) =>request_signal(3),
421	request(4) =>request_signal(4)
422	);
423
424	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
425	GENERIC MAP(number_of_ports =>4)
426	PORT MAP(
427	data_in => Port2_in,
428	data_in_en => data_in_en(2),
429	reset => reset,
430	clk =>clk,
431	grant(5) => grant_signal(5),
432	grant(6) => grant_signal(6),
433	grant(7) => grant_signal(7),
434	grant(8) => grant_signal(8),
435	fifo_full =>fifo_in_full(2),
436	priority_rotation => priority_rotation_signal(2),
437	fifo_empty => fifo_in_empty(2),
438	data_out =>crossbar_in_port2,
439	data_out_pulse =>crossbar_in_pulse2,
440	request(5) =>request_signal(5),
441	request(6) =>request_signal(6),
442	request(7) =>request_signal(7),
443	request(8) =>request_signal(8)
444	);
445
446	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
447	GENERIC MAP(number_of_ports =>4)
448	PORT MAP(
449	data_in => Port3_in,
450	data_in_en => data_in_en(3),
451	reset => reset,
452	clk =>clk,
453	grant(9) => grant_signal(9),
454	grant(10) => grant_signal(10),
455	grant(11) => grant_signal(11),
456	grant(12) => grant_signal(12),
457	fifo_full =>fifo_in_full(3),
458	priority_rotation => priority_rotation_signal(3),
459	fifo_empty => fifo_in_empty(3),
460	data_out =>crossbar_in_port3,
461	data_out_pulse =>crossbar_in_pulse3,
462	request(9) =>request_signal(9),
463	request(10) =>request_signal(10),
464	request(11) =>request_signal(11),
465	request(12) =>request_signal(12)
466	);
467
468	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
469	GENERIC MAP(number_of_ports =>4)
470	PORT MAP(
471	data_in => Port4_in,
472	data_in_en => data_in_en(4),
473	reset => reset,
474	clk =>clk,
475	grant(13) => grant_signal(13),
476	grant(14) => grant_signal(14),
477	grant(15) => grant_signal(15),
478	grant(16) => grant_signal(16),
479	fifo_full =>fifo_in_full(4),
480	priority_rotation => priority_rotation_signal(4),
481	fifo_empty => fifo_in_empty(4),
482	data_out =>crossbar_in_port4,
483	data_out_pulse =>crossbar_in_pulse4,
484	request(13) =>request_signal(13),
485	request(14) =>request_signal(14),
486	request(15) =>request_signal(15),
487	request(16) =>request_signal(16)
488	);
489
490	end generate switch4x4;
491
492
493	-- switch 5 ports
494	switch5x5 : if number_of_ports = 5 generate
495
496	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
497	GENERIC MAP(number_of_ports =>5)
498	PORT MAP(
499	data_in => Port1_in,
500	data_in_en => data_in_en(1),
501	reset => reset,
502	clk =>clk,
503	grant(1) => grant_signal(1),
504	grant(2) => grant_signal(2),
505	grant(3) => grant_signal(3),
506	grant(4) => grant_signal(4),
507	grant(5) => grant_signal(5),
508	fifo_full =>fifo_in_full(1),
509	priority_rotation => priority_rotation_signal(1),
510	fifo_empty => fifo_in_empty(1),
511	data_out =>crossbar_in_port1,
512	data_out_pulse =>crossbar_in_pulse1,
513	request(1) =>request_signal(1),
514	request(2) =>request_signal(2),
515	request(3) =>request_signal(3),
516	request(4) =>request_signal(4),
517	request(5) =>request_signal(5)
518	);
519
520	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
521	GENERIC MAP(number_of_ports =>5)
522	PORT MAP(
523	data_in => Port2_in,
524	data_in_en => data_in_en(2),
525	reset => reset,
526	clk =>clk,
527	grant(6) => grant_signal(6),
528	grant(7) => grant_signal(7),
529	grant(8) => grant_signal(8),
530	grant(9) => grant_signal(9),
531	grant(10) => grant_signal(10),
532	fifo_full =>fifo_in_full(2),
533	priority_rotation => priority_rotation_signal(2),
534	fifo_empty => fifo_in_empty(2),
535	data_out =>crossbar_in_port2,
536	data_out_pulse =>crossbar_in_pulse2,
537	request(6) =>request_signal(6),
538	request(7) =>request_signal(7),
539	request(8) =>request_signal(8),
540	request(9) =>request_signal(9),
541	request(10) =>request_signal(10)
542	);
543
544	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
545	GENERIC MAP(number_of_ports =>5)
546	PORT MAP(
547	data_in => Port3_in,
548	data_in_en => data_in_en(3),
549	reset => reset,
550	clk =>clk,
551	grant(11) => grant_signal(11),
552	grant(12) => grant_signal(12),
553	grant(13) => grant_signal(13),
554	grant(14) => grant_signal(14),
555	grant(15) => grant_signal(15),
556	fifo_full =>fifo_in_full(3),
557	priority_rotation => priority_rotation_signal(3),
558	fifo_empty => fifo_in_empty(3),
559	data_out =>crossbar_in_port3,
560	data_out_pulse =>crossbar_in_pulse3,
561	request(11) =>request_signal(11),
562	request(12) =>request_signal(12),
563	request(13) =>request_signal(13),
564	request(14) =>request_signal(14),
565	request(15) =>request_signal(15)
566	);
567
568	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
569	GENERIC MAP(number_of_ports =>5)
570	PORT MAP(
571	data_in => Port4_in,
572	data_in_en => data_in_en(4),
573	reset => reset,
574	clk =>clk,
575	grant(16) => grant_signal(16),
576	grant(17) => grant_signal(17),
577	grant(18) => grant_signal(18),
578	grant(19) => grant_signal(19),
579	grant(20) => grant_signal(20),
580	fifo_full =>fifo_in_full(4),
581	priority_rotation => priority_rotation_signal(4),
582	fifo_empty => fifo_in_empty(4),
583	data_out =>crossbar_in_port4,
584	data_out_pulse =>crossbar_in_pulse4,
585	request(16) =>request_signal(16),
586	request(17) =>request_signal(17),
587	request(18) =>request_signal(18),
588	request(19) =>request_signal(19),
589	request(20) =>request_signal(20)
590	);
591
592	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
593	GENERIC MAP(number_of_ports =>5)
594	PORT MAP(
595	data_in => Port5_in,
596	data_in_en => data_in_en(5),
597	reset => reset,
598	clk =>clk,
599	grant(21) => grant_signal(21),
600	grant(22) => grant_signal(22),
601	grant(23) => grant_signal(23),
602	grant(24) => grant_signal(24),
603	grant(25) => grant_signal(25),
604	fifo_full =>fifo_in_full(5),
605	priority_rotation => priority_rotation_signal(5),
606	fifo_empty => fifo_in_empty(5),
607	data_out =>crossbar_in_port5,
608	data_out_pulse =>crossbar_in_pulse5,
609	request(21) =>request_signal(21),
610	request(22) =>request_signal(22),
611	request(23) =>request_signal(23),
612	request(24) =>request_signal(24),
613	request(25) =>request_signal(25)
614	);
615
616	end generate switch5x5;
617
618
619	-- switch 6 ports
620	switch6x6 : if number_of_ports = 6 generate
621
622	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
623	GENERIC MAP(number_of_ports =>6)
624	PORT MAP(
625	data_in => Port1_in,
626	data_in_en => data_in_en(1),
627	reset => reset,
628	clk =>clk,
629	grant(1) => grant_signal(1),
630	grant(2) => grant_signal(2),
631	grant(3) => grant_signal(3),
632	grant(4) => grant_signal(4),
633	grant(5) => grant_signal(5),
634	grant(6) => grant_signal(6),
635	fifo_full =>fifo_in_full(1),
636	priority_rotation => priority_rotation_signal(1),
637	fifo_empty => fifo_in_empty(1),
638	data_out =>crossbar_in_port1,
639	data_out_pulse =>crossbar_in_pulse1,
640	request(1) =>request_signal(1),
641	request(2) =>request_signal(2),
642	request(3) =>request_signal(3),
643	request(4) =>request_signal(4),
644	request(5) =>request_signal(5),
645	request(6) =>request_signal(6)
646	);
647
648	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
649	GENERIC MAP(number_of_ports =>6)
650	PORT MAP(
651	data_in => Port2_in,
652	data_in_en => data_in_en(2),
653	reset => reset,
654	clk =>clk,
655	grant(7) => grant_signal(7),
656	grant(8) => grant_signal(8),
657	grant(9) => grant_signal(9),
658	grant(10) => grant_signal(10),
659	grant(11) => grant_signal(11),
660	grant(12) => grant_signal(12),
661	fifo_full =>fifo_in_full(2),
662	priority_rotation => priority_rotation_signal(2),
663	fifo_empty => fifo_in_empty(2),
664	data_out =>crossbar_in_port2,
665	data_out_pulse =>crossbar_in_pulse2,
666	request(7) =>request_signal(7),
667	request(8) =>request_signal(8),
668	request(9) =>request_signal(9),
669	request(10) =>request_signal(10),
670	request(11) =>request_signal(11),
671	request(12) =>request_signal(12)
672	);
673
674	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
675	GENERIC MAP(number_of_ports =>6)
676	PORT MAP(
677	data_in => Port3_in,
678	data_in_en => data_in_en(3),
679	reset => reset,
680	clk =>clk,
681	grant(13) => grant_signal(13),
682	grant(14) => grant_signal(14),
683	grant(15) => grant_signal(15),
684	grant(16) => grant_signal(16),
685	grant(17) => grant_signal(17),
686	grant(18) => grant_signal(18),
687	fifo_full =>fifo_in_full(3),
688	priority_rotation => priority_rotation_signal(3),
689	fifo_empty => fifo_in_empty(3),
690	data_out =>crossbar_in_port3,
691	data_out_pulse =>crossbar_in_pulse3,
692	request(13) =>request_signal(13),
693	request(14) =>request_signal(14),
694	request(15) =>request_signal(15),
695	request(16) =>request_signal(16),
696	request(17) =>request_signal(17),
697	request(18) =>request_signal(18)
698	);
699
700	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
701	GENERIC MAP(number_of_ports =>6)
702	PORT MAP(
703	data_in => Port4_in,
704	data_in_en => data_in_en(4),
705	reset => reset,
706	clk =>clk,
707	grant(19) => grant_signal(19),
708	grant(20) => grant_signal(20),
709	grant(21) => grant_signal(21),
710	grant(22) => grant_signal(22),
711	grant(23) => grant_signal(23),
712	grant(24) => grant_signal(24),
713	fifo_full =>fifo_in_full(4),
714	priority_rotation => priority_rotation_signal(4),
715	fifo_empty => fifo_in_empty(4),
716	data_out =>crossbar_in_port4,
717	data_out_pulse =>crossbar_in_pulse4,
718	request(19) =>request_signal(19),
719	request(20) =>request_signal(20),
720	request(21) =>request_signal(21),
721	request(22) =>request_signal(22),
722	request(23) =>request_signal(23),
723	request(24) =>request_signal(24)
724	);
725
726	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
727	GENERIC MAP(number_of_ports =>6)
728	PORT MAP(
729	data_in => Port5_in,
730	data_in_en => data_in_en(5),
731	reset => reset,
732	clk =>clk,
733	grant(25) => grant_signal(25),
734	grant(26) => grant_signal(26),
735	grant(27) => grant_signal(27),
736	grant(28) => grant_signal(28),
737	grant(29) => grant_signal(29),
738	grant(30) => grant_signal(30),
739	fifo_full =>fifo_in_full(5),
740	priority_rotation => priority_rotation_signal(5),
741	fifo_empty => fifo_in_empty(5),
742	data_out =>crossbar_in_port5,
743	data_out_pulse =>crossbar_in_pulse5,
744	request(25) =>request_signal(25),
745	request(26) =>request_signal(26),
746	request(27) =>request_signal(27),
747	request(28) =>request_signal(28),
748	request(29) =>request_signal(29),
749	request(30) =>request_signal(30)
750	);
751
752	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
753	GENERIC MAP(number_of_ports =>6)
754	PORT MAP(
755	data_in => Port6_in,
756	data_in_en => data_in_en(6),
757	reset => reset,
758	clk =>clk,
759	grant(31) => grant_signal(31),
760	grant(32) => grant_signal(32),
761	grant(33) => grant_signal(33),
762	grant(34) => grant_signal(34),
763	grant(35) => grant_signal(35),
764	grant(36) => grant_signal(36),
765	fifo_full =>fifo_in_full(6),
766	priority_rotation => priority_rotation_signal(6),
767	fifo_empty => fifo_in_empty(6),
768	data_out =>crossbar_in_port6,
769	data_out_pulse =>crossbar_in_pulse6,
770	request(31) =>request_signal(31),
771	request(32) =>request_signal(32),
772	request(33) =>request_signal(33),
773	request(34) =>request_signal(34),
774	request(35) =>request_signal(35),
775	request(36) =>request_signal(36)
776	);
777
778	end generate switch6x6;
779
780
781	-- switch 7 ports
782	switch7x7 : if number_of_ports = 7 generate
783
784	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
785	GENERIC MAP(number_of_ports =>7)
786	PORT MAP(
787	data_in => Port1_in,
788	data_in_en => data_in_en(1),
789	reset => reset,
790	clk =>clk,
791	grant(1) => grant_signal(1),
792	grant(2) => grant_signal(2),
793	grant(3) => grant_signal(3),
794	grant(4) => grant_signal(4),
795	grant(5) => grant_signal(5),
796	grant(6) => grant_signal(6),
797	grant(7) => grant_signal(7),
798	fifo_full =>fifo_in_full(1),
799	priority_rotation => priority_rotation_signal(1),
800	fifo_empty => fifo_in_empty(1),
801	data_out =>crossbar_in_port1,
802	data_out_pulse =>crossbar_in_pulse1,
803	request(1) =>request_signal(1),
804	request(2) =>request_signal(2),
805	request(3) =>request_signal(3),
806	request(4) =>request_signal(4),
807	request(5) =>request_signal(5),
808	request(6) =>request_signal(6),
809	request(7) =>request_signal(7)
810	);
811
812	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
813	GENERIC MAP(number_of_ports =>7)
814	PORT MAP(
815	data_in => Port2_in,
816	data_in_en => data_in_en(2),
817	reset => reset,
818	clk =>clk,
819	grant(8) => grant_signal(8),
820	grant(9) => grant_signal(9),
821	grant(10) => grant_signal(10),
822	grant(11) => grant_signal(11),
823	grant(12) => grant_signal(12),
824	grant(13) => grant_signal(13),
825	grant(14) => grant_signal(14),
826	fifo_full =>fifo_in_full(2),
827	priority_rotation => priority_rotation_signal(2),
828	fifo_empty => fifo_in_empty(2),
829	data_out =>crossbar_in_port2,
830	data_out_pulse =>crossbar_in_pulse2,
831	request(8) =>request_signal(8),
832	request(9) =>request_signal(9),
833	request(10) =>request_signal(10),
834	request(11) =>request_signal(11),
835	request(12) =>request_signal(12),
836	request(13) =>request_signal(13),
837	request(14) =>request_signal(14)
838	);
839
840	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
841	GENERIC MAP(number_of_ports =>7)
842	PORT MAP(
843	data_in => Port3_in,
844	data_in_en => data_in_en(3),
845	reset => reset,
846	clk =>clk,
847	grant(15) => grant_signal(15),
848	grant(16) => grant_signal(16),
849	grant(17) => grant_signal(17),
850	grant(18) => grant_signal(18),
851	grant(19) => grant_signal(19),
852	grant(20) => grant_signal(20),
853	grant(21) => grant_signal(21),
854	fifo_full =>fifo_in_full(3),
855	priority_rotation => priority_rotation_signal(3),
856	fifo_empty => fifo_in_empty(3),
857	data_out =>crossbar_in_port3,
858	data_out_pulse =>crossbar_in_pulse3,
859	request(15) =>request_signal(15),
860	request(16) =>request_signal(16),
861	request(17) =>request_signal(17),
862	request(18) =>request_signal(18),
863	request(19) =>request_signal(19),
864	request(20) =>request_signal(20),
865	request(21) =>request_signal(21)
866	);
867
868	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
869	GENERIC MAP(number_of_ports =>7)
870	PORT MAP(
871	data_in => Port4_in,
872	data_in_en => data_in_en(4),
873	reset => reset,
874	clk =>clk,
875	grant(22) => grant_signal(22),
876	grant(23) => grant_signal(23),
877	grant(24) => grant_signal(24),
878	grant(25) => grant_signal(25),
879	grant(26) => grant_signal(26),
880	grant(27) => grant_signal(27),
881	grant(28) => grant_signal(28),
882	fifo_full =>fifo_in_full(4),
883	priority_rotation => priority_rotation_signal(4),
884	fifo_empty => fifo_in_empty(4),
885	data_out =>crossbar_in_port4,
886	data_out_pulse =>crossbar_in_pulse4,
887	request(22) =>request_signal(22),
888	request(23) =>request_signal(23),
889	request(24) =>request_signal(24),
890	request(25) =>request_signal(25),
891	request(26) =>request_signal(26),
892	request(27) =>request_signal(27),
893	request(28) =>request_signal(28)
894	);
895
896	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
897	GENERIC MAP(number_of_ports =>7)
898	PORT MAP(
899	data_in => Port5_in,
900	data_in_en => data_in_en(5),
901	reset => reset,
902	clk =>clk,
903	grant(29) => grant_signal(29),
904	grant(30) => grant_signal(30),
905	grant(31) => grant_signal(31),
906	grant(32) => grant_signal(32),
907	grant(33) => grant_signal(33),
908	grant(34) => grant_signal(34),
909	grant(35) => grant_signal(35),
910	fifo_full =>fifo_in_full(5),
911	priority_rotation => priority_rotation_signal(5),
912	fifo_empty => fifo_in_empty(5),
913	data_out =>crossbar_in_port5,
914	data_out_pulse =>crossbar_in_pulse5,
915	request(29) =>request_signal(29),
916	request(30) =>request_signal(30),
917	request(31) =>request_signal(31),
918	request(32) =>request_signal(32),
919	request(33) =>request_signal(33),
920	request(34) =>request_signal(34),
921	request(35) =>request_signal(35)
922	);
923
924	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
925	GENERIC MAP(number_of_ports =>7)
926	PORT MAP(
927	data_in => Port6_in,
928	data_in_en => data_in_en(6),
929	reset => reset,
930	clk =>clk,
931	grant(36) => grant_signal(36),
932	grant(37) => grant_signal(37),
933	grant(38) => grant_signal(38),
934	grant(39) => grant_signal(39),
935	grant(40) => grant_signal(40),
936	grant(41) => grant_signal(41),
937	grant(42) => grant_signal(42),
938	fifo_full =>fifo_in_full(6),
939	priority_rotation => priority_rotation_signal(6),
940	fifo_empty => fifo_in_empty(6),
941	data_out =>crossbar_in_port6,
942	data_out_pulse =>crossbar_in_pulse6,
943	request(36) =>request_signal(36),
944	request(37) =>request_signal(37),
945	request(38) =>request_signal(38),
946	request(39) =>request_signal(39),
947	request(40) =>request_signal(40),
948	request(41) =>request_signal(41),
949	request(42) =>request_signal(42)
950	);
951
952	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
953	GENERIC MAP(number_of_ports =>7)
954	PORT MAP(
955	data_in => Port7_in,
956	data_in_en => data_in_en(7),
957	reset => reset,
958	clk =>clk,
959	grant(43) => grant_signal(43),
960	grant(44) => grant_signal(44),
961	grant(45) => grant_signal(45),
962	grant(46) => grant_signal(46),
963	grant(47) => grant_signal(47),
964	grant(48) => grant_signal(48),
965	grant(49) => grant_signal(49),
966	fifo_full =>fifo_in_full(7),
967	priority_rotation => priority_rotation_signal(7),
968	fifo_empty => fifo_in_empty(7),
969	data_out =>crossbar_in_port7,
970	data_out_pulse =>crossbar_in_pulse7,
971	request(43) =>request_signal(43),
972	request(44) =>request_signal(44),
973	request(45) =>request_signal(45),
974	request(46) =>request_signal(46),
975	request(47) =>request_signal(47),
976	request(48) =>request_signal(48),
977	request(49) =>request_signal(49)
978	);
979
980	end generate switch7x7;
981
982
983	-- switch 8 ports
984	switch8x8 : if number_of_ports = 8 generate
985
986	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
987	GENERIC MAP(number_of_ports =>8)
988	PORT MAP(
989	data_in => Port1_in,
990	data_in_en => data_in_en(1),
991	reset => reset,
992	clk =>clk,
993	grant(1) => grant_signal(1),
994	grant(2) => grant_signal(2),
995	grant(3) => grant_signal(3),
996	grant(4) => grant_signal(4),
997	grant(5) => grant_signal(5),
998	grant(6) => grant_signal(6),
999	grant(7) => grant_signal(7),
1000	grant(8) => grant_signal(8),
1001	fifo_full =>fifo_in_full(1),
1002	priority_rotation => priority_rotation_signal(1),
1003	fifo_empty => fifo_in_empty(1),
1004	data_out =>crossbar_in_port1,
1005	data_out_pulse =>crossbar_in_pulse1,
1006	request(1) =>request_signal(1),
1007	request(2) =>request_signal(2),
1008	request(3) =>request_signal(3),
1009	request(4) =>request_signal(4),
1010	request(5) =>request_signal(5),
1011	request(6) =>request_signal(6),
1012	request(7) =>request_signal(7),
1013	request(8) =>request_signal(8)
1014	);
1015
1016	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1017	GENERIC MAP(number_of_ports =>8)
1018	PORT MAP(
1019	data_in => Port2_in,
1020	data_in_en => data_in_en(2),
1021	reset => reset,
1022	clk =>clk,
1023	grant(1) => grant_signal(9),
1024	grant(2) => grant_signal(10),
1025	grant(3) => grant_signal(11),
1026	grant(4) => grant_signal(12),
1027	grant(5) => grant_signal(13),
1028	grant(6) => grant_signal(14),
1029	grant(7) => grant_signal(15),
1030	grant(8) => grant_signal(16),
1031	fifo_full =>fifo_in_full(2),
1032	priority_rotation => priority_rotation_signal(2),
1033	fifo_empty => fifo_in_empty(2),
1034	data_out =>crossbar_in_port2,
1035	data_out_pulse =>crossbar_in_pulse2,
1036	request(1) =>request_signal(9),
1037	request(2) =>request_signal(10),
1038	request(3) =>request_signal(11),
1039	request(4) =>request_signal(12),
1040	request(5) =>request_signal(13),
1041	request(6) =>request_signal(14),
1042	request(7) =>request_signal(15),
1043	request(8) =>request_signal(16)
1044	);
1045
1046	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1047	GENERIC MAP(number_of_ports =>8)
1048	PORT MAP(
1049	data_in => Port3_in,
1050	data_in_en => data_in_en(3),
1051	reset => reset,
1052	clk =>clk,
1053	grant(1) => grant_signal(17),
1054	grant(2) => grant_signal(18),
1055	grant(3) => grant_signal(19),
1056	grant(4) => grant_signal(20),
1057	grant(5) => grant_signal(21),
1058	grant(6) => grant_signal(22),
1059	grant(7) => grant_signal(23),
1060	grant(8) => grant_signal(24),
1061	fifo_full =>fifo_in_full(3),
1062	priority_rotation => priority_rotation_signal(3),
1063	fifo_empty => fifo_in_empty(3),
1064	data_out =>crossbar_in_port3,
1065	data_out_pulse =>crossbar_in_pulse3,
1066	request(1) =>request_signal(17),
1067	request(2) =>request_signal(18),
1068	request(3) =>request_signal(19),
1069	request(4) =>request_signal(20),
1070	request(5) =>request_signal(21),
1071	request(6) =>request_signal(22),
1072	request(7) =>request_signal(23),
1073	request(8) =>request_signal(24)
1074	);
1075
1076	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1077	GENERIC MAP(number_of_ports =>8)
1078	PORT MAP(
1079	data_in => Port4_in,
1080	data_in_en => data_in_en(4),
1081	reset => reset,
1082	clk =>clk,
1083	grant(1) => grant_signal(25),
1084	grant(2) => grant_signal(26),
1085	grant(3) => grant_signal(27),
1086	grant(4) => grant_signal(28),
1087	grant(5) => grant_signal(29),
1088	grant(6) => grant_signal(30),
1089	grant(7) => grant_signal(31),
1090	grant(8) => grant_signal(32),
1091	fifo_full =>fifo_in_full(4),
1092	priority_rotation => priority_rotation_signal(4),
1093	fifo_empty => fifo_in_empty(4),
1094	data_out =>crossbar_in_port4,
1095	data_out_pulse =>crossbar_in_pulse4,
1096	request(1) =>request_signal(25),
1097	request(2) =>request_signal(26),
1098	request(3) =>request_signal(27),
1099	request(4) =>request_signal(28),
1100	request(5) =>request_signal(29),
1101	request(6) =>request_signal(30),
1102	request(7) =>request_signal(31),
1103	request(8) =>request_signal(32)
1104	);
1105
1106	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1107	GENERIC MAP(number_of_ports =>8)
1108	PORT MAP(
1109	data_in => Port5_in,
1110	data_in_en => data_in_en(5),
1111	reset => reset,
1112	clk =>clk,
1113	grant(1) => grant_signal(33),
1114	grant(2) => grant_signal(34),
1115	grant(3) => grant_signal(35),
1116	grant(4) => grant_signal(36),
1117	grant(5) => grant_signal(37),
1118	grant(6) => grant_signal(38),
1119	grant(7) => grant_signal(39),
1120	grant(8) => grant_signal(40),
1121	fifo_full =>fifo_in_full(5),
1122	priority_rotation => priority_rotation_signal(5),
1123	fifo_empty => fifo_in_empty(5),
1124	data_out =>crossbar_in_port5,
1125	data_out_pulse =>crossbar_in_pulse5,
1126	request(1) =>request_signal(33),
1127	request(2) =>request_signal(34),
1128	request(3) =>request_signal(35),
1129	request(4) =>request_signal(36),
1130	request(5) =>request_signal(37),
1131	request(6) =>request_signal(38),
1132	request(7) =>request_signal(39),
1133	request(8) =>request_signal(40)
1134	);
1135
1136	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1137	GENERIC MAP(number_of_ports =>8)
1138	PORT MAP(
1139	data_in => Port6_in,
1140	data_in_en => data_in_en(6),
1141	reset => reset,
1142	clk =>clk,
1143	grant(1) => grant_signal(41),
1144	grant(2) => grant_signal(42),
1145	grant(3) => grant_signal(43),
1146	grant(4) => grant_signal(44),
1147	grant(5) => grant_signal(45),
1148	grant(6) => grant_signal(46),
1149	grant(7) => grant_signal(47),
1150	grant(8) => grant_signal(48),
1151	fifo_full =>fifo_in_full(6),
1152	priority_rotation => priority_rotation_signal(6),
1153	fifo_empty => fifo_in_empty(6),
1154	data_out =>crossbar_in_port6,
1155	data_out_pulse =>crossbar_in_pulse6,
1156	request(1) =>request_signal(41),
1157	request(2) =>request_signal(42),
1158	request(3) =>request_signal(43),
1159	request(4) =>request_signal(44),
1160	request(5) =>request_signal(45),
1161	request(6) =>request_signal(46),
1162	request(7) =>request_signal(47),
1163	request(8) =>request_signal(48)
1164	);
1165
1166	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1167	GENERIC MAP(number_of_ports =>8)
1168	PORT MAP(
1169	data_in => Port7_in,
1170	data_in_en => data_in_en(7),
1171	reset => reset,
1172	clk =>clk,
1173	grant(1) => grant_signal(49),
1174	grant(2) => grant_signal(50),
1175	grant(3) => grant_signal(51),
1176	grant(4) => grant_signal(52),
1177	grant(5) => grant_signal(53),
1178	grant(6) => grant_signal(54),
1179	grant(7) => grant_signal(55),
1180	grant(8) => grant_signal(56),
1181	fifo_full =>fifo_in_full(7),
1182	priority_rotation => priority_rotation_signal(7),
1183	fifo_empty => fifo_in_empty(7),
1184	data_out =>crossbar_in_port7,
1185	data_out_pulse =>crossbar_in_pulse7,
1186	request(1) =>request_signal(49),
1187	request(2) =>request_signal(50),
1188	request(3) =>request_signal(51),
1189	request(4) =>request_signal(52),
1190	request(5) =>request_signal(53),
1191	request(6) =>request_signal(54),
1192	request(7) =>request_signal(55),
1193	request(8) =>request_signal(56)
1194	);
1195
1196	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1197	GENERIC MAP(number_of_ports =>8)
1198	PORT MAP(
1199	data_in => Port8_in,
1200	data_in_en => data_in_en(8),
1201	reset => reset,
1202	clk =>clk,
1203	grant(1) => grant_signal(57),
1204	grant(2) => grant_signal(58),
1205	grant(3) => grant_signal(59),
1206	grant(4) => grant_signal(60),
1207	grant(5) => grant_signal(61),
1208	grant(6) => grant_signal(62),
1209	grant(7) => grant_signal(63),
1210	grant(8) => grant_signal(64),
1211	fifo_full =>fifo_in_full(8),
1212	priority_rotation => priority_rotation_signal(8),
1213	fifo_empty => fifo_in_empty(8),
1214	data_out =>crossbar_in_port8,
1215	data_out_pulse =>crossbar_in_pulse8,
1216	request(1) =>request_signal(57),
1217	request(2) =>request_signal(58),
1218	request(3) =>request_signal(59),
1219	request(4) =>request_signal(60),
1220	request(5) =>request_signal(61),
1221	request(6) =>request_signal(62),
1222	request(7) =>request_signal(63),
1223	request(8) =>request_signal(64)
1224	);
1225
1226	end generate switch8x8;
1227
1228
1229	-- switch 9 ports
1230	switch9x9 : if number_of_ports = 9 generate
1231
1232	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1233	GENERIC MAP(number_of_ports =>9)
1234	PORT MAP(
1235	data_in => Port1_in,
1236	data_in_en => data_in_en(1),
1237	reset => reset,
1238	clk =>clk,
1239	grant(1) => grant_signal(1),
1240	grant(2) => grant_signal(2),
1241	grant(3) => grant_signal(3),
1242	grant(4) => grant_signal(4),
1243	grant(5) => grant_signal(5),
1244	grant(6) => grant_signal(6),
1245	grant(7) => grant_signal(7),
1246	grant(8) => grant_signal(8),
1247	grant(9) => grant_signal(9),
1248	fifo_full =>fifo_in_full(1),
1249	priority_rotation => priority_rotation_signal(1),
1250	fifo_empty => fifo_in_empty(1),
1251	data_out =>crossbar_in_port1,
1252	data_out_pulse =>crossbar_in_pulse1,
1253	request(1) =>request_signal(1),
1254	request(2) =>request_signal(2),
1255	request(3) =>request_signal(3),
1256	request(4) =>request_signal(4),
1257	request(5) =>request_signal(5),
1258	request(6) =>request_signal(6),
1259	request(7) =>request_signal(7),
1260	request(8) =>request_signal(8),
1261	request(9) =>request_signal(9)
1262	);
1263
1264	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1265	GENERIC MAP(number_of_ports =>9)
1266	PORT MAP(
1267	data_in => Port2_in,
1268	data_in_en => data_in_en(2),
1269	reset => reset,
1270	clk =>clk,
1271	grant(10) => grant_signal(10),
1272	grant(11) => grant_signal(11),
1273	grant(12) => grant_signal(12),
1274	grant(13) => grant_signal(13),
1275	grant(14) => grant_signal(14),
1276	grant(15) => grant_signal(15),
1277	grant(16) => grant_signal(16),
1278	grant(17) => grant_signal(17),
1279	grant(18) => grant_signal(18),
1280	fifo_full =>fifo_in_full(2),
1281	priority_rotation => priority_rotation_signal(2),
1282	fifo_empty => fifo_in_empty(2),
1283	data_out =>crossbar_in_port2,
1284	data_out_pulse =>crossbar_in_pulse2,
1285	request(10) =>request_signal(10),
1286	request(11) =>request_signal(11),
1287	request(12) =>request_signal(12),
1288	request(13) =>request_signal(13),
1289	request(14) =>request_signal(14),
1290	request(15) =>request_signal(15),
1291	request(16) =>request_signal(16),
1292	request(17) =>request_signal(17),
1293	request(18) =>request_signal(18)
1294	);
1295
1296	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1297	GENERIC MAP(number_of_ports =>9)
1298	PORT MAP(
1299	data_in => Port3_in,
1300	data_in_en => data_in_en(3),
1301	reset => reset,
1302	clk =>clk,
1303	grant(19) => grant_signal(19),
1304	grant(20) => grant_signal(20),
1305	grant(21) => grant_signal(21),
1306	grant(22) => grant_signal(22),
1307	grant(23) => grant_signal(23),
1308	grant(24) => grant_signal(24),
1309	grant(25) => grant_signal(25),
1310	grant(26) => grant_signal(26),
1311	grant(27) => grant_signal(27),
1312	fifo_full =>fifo_in_full(3),
1313	priority_rotation => priority_rotation_signal(3),
1314	fifo_empty => fifo_in_empty(3),
1315	data_out =>crossbar_in_port3,
1316	data_out_pulse =>crossbar_in_pulse3,
1317	request(19) =>request_signal(19),
1318	request(20) =>request_signal(20),
1319	request(21) =>request_signal(21),
1320	request(22) =>request_signal(22),
1321	request(23) =>request_signal(23),
1322	request(24) =>request_signal(24),
1323	request(25) =>request_signal(25),
1324	request(26) =>request_signal(26),
1325	request(27) =>request_signal(27)
1326	);
1327
1328	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1329	GENERIC MAP(number_of_ports =>9)
1330	PORT MAP(
1331	data_in => Port4_in,
1332	data_in_en => data_in_en(4),
1333	reset => reset,
1334	clk =>clk,
1335	grant(28) => grant_signal(28),
1336	grant(29) => grant_signal(29),
1337	grant(30) => grant_signal(30),
1338	grant(31) => grant_signal(31),
1339	grant(32) => grant_signal(32),
1340	grant(33) => grant_signal(33),
1341	grant(34) => grant_signal(34),
1342	grant(35) => grant_signal(35),
1343	grant(36) => grant_signal(36),
1344	fifo_full =>fifo_in_full(4),
1345	priority_rotation => priority_rotation_signal(4),
1346	fifo_empty => fifo_in_empty(4),
1347	data_out =>crossbar_in_port4,
1348	data_out_pulse =>crossbar_in_pulse4,
1349	request(28) =>request_signal(28),
1350	request(29) =>request_signal(29),
1351	request(30) =>request_signal(30),
1352	request(31) =>request_signal(31),
1353	request(32) =>request_signal(32),
1354	request(33) =>request_signal(33),
1355	request(34) =>request_signal(34),
1356	request(35) =>request_signal(35),
1357	request(36) =>request_signal(36)
1358	);
1359
1360	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1361	GENERIC MAP(number_of_ports =>9)
1362	PORT MAP(
1363	data_in => Port5_in,
1364	data_in_en => data_in_en(5),
1365	reset => reset,
1366	clk =>clk,
1367	grant(37) => grant_signal(37),
1368	grant(38) => grant_signal(38),
1369	grant(39) => grant_signal(39),
1370	grant(40) => grant_signal(40),
1371	grant(41) => grant_signal(41),
1372	grant(42) => grant_signal(42),
1373	grant(43) => grant_signal(43),
1374	grant(44) => grant_signal(44),
1375	grant(45) => grant_signal(45),
1376	fifo_full =>fifo_in_full(5),
1377	priority_rotation => priority_rotation_signal(5),
1378	fifo_empty => fifo_in_empty(5),
1379	data_out =>crossbar_in_port5,
1380	data_out_pulse =>crossbar_in_pulse5,
1381	request(37) =>request_signal(37),
1382	request(38) =>request_signal(38),
1383	request(39) =>request_signal(39),
1384	request(40) =>request_signal(40),
1385	request(41) =>request_signal(41),
1386	request(42) =>request_signal(42),
1387	request(43) =>request_signal(43),
1388	request(44) =>request_signal(44),
1389	request(45) =>request_signal(45)
1390	);
1391
1392	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1393	GENERIC MAP(number_of_ports =>9)
1394	PORT MAP(
1395	data_in => Port6_in,
1396	data_in_en => data_in_en(6),
1397	reset => reset,
1398	clk =>clk,
1399	grant(46) => grant_signal(46),
1400	grant(47) => grant_signal(47),
1401	grant(48) => grant_signal(48),
1402	grant(49) => grant_signal(49),
1403	grant(50) => grant_signal(50),
1404	grant(51) => grant_signal(51),
1405	grant(52) => grant_signal(52),
1406	grant(53) => grant_signal(53),
1407	grant(54) => grant_signal(54),
1408	fifo_full =>fifo_in_full(6),
1409	priority_rotation => priority_rotation_signal(6),
1410	fifo_empty => fifo_in_empty(6),
1411	data_out =>crossbar_in_port6,
1412	data_out_pulse =>crossbar_in_pulse6,
1413	request(46) =>request_signal(46),
1414	request(47) =>request_signal(47),
1415	request(48) =>request_signal(48),
1416	request(49) =>request_signal(49),
1417	request(50) =>request_signal(50),
1418	request(51) =>request_signal(51),
1419	request(52) =>request_signal(52),
1420	request(53) =>request_signal(53),
1421	request(54) =>request_signal(54)
1422	);
1423
1424	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1425	GENERIC MAP(number_of_ports =>9)
1426	PORT MAP(
1427	data_in => Port7_in,
1428	data_in_en => data_in_en(7),
1429	reset => reset,
1430	clk =>clk,
1431	grant(55) => grant_signal(55),
1432	grant(56) => grant_signal(56),
1433	grant(57) => grant_signal(57),
1434	grant(58) => grant_signal(58),
1435	grant(59) => grant_signal(59),
1436	grant(60) => grant_signal(60),
1437	grant(61) => grant_signal(61),
1438	grant(62) => grant_signal(62),
1439	grant(63) => grant_signal(63),
1440	fifo_full =>fifo_in_full(7),
1441	priority_rotation => priority_rotation_signal(7),
1442	fifo_empty => fifo_in_empty(7),
1443	data_out =>crossbar_in_port7,
1444	data_out_pulse =>crossbar_in_pulse7,
1445	request(55) =>request_signal(55),
1446	request(56) =>request_signal(56),
1447	request(57) =>request_signal(57),
1448	request(58) =>request_signal(58),
1449	request(59) =>request_signal(59),
1450	request(60) =>request_signal(60),
1451	request(61) =>request_signal(61),
1452	request(62) =>request_signal(62),
1453	request(63) =>request_signal(63)
1454	);
1455
1456	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1457	GENERIC MAP(number_of_ports =>9)
1458	PORT MAP(
1459	data_in => Port8_in,
1460	data_in_en => data_in_en(8),
1461	reset => reset,
1462	clk =>clk,
1463	grant(64) => grant_signal(64),
1464	grant(65) => grant_signal(65),
1465	grant(66) => grant_signal(66),
1466	grant(67) => grant_signal(67),
1467	grant(68) => grant_signal(68),
1468	grant(69) => grant_signal(69),
1469	grant(70) => grant_signal(70),
1470	grant(71) => grant_signal(71),
1471	grant(72) => grant_signal(72),
1472	fifo_full =>fifo_in_full(8),
1473	priority_rotation => priority_rotation_signal(8),
1474	fifo_empty => fifo_in_empty(8),
1475	data_out =>crossbar_in_port8,
1476	data_out_pulse =>crossbar_in_pulse8,
1477	request(64) =>request_signal(64),
1478	request(65) =>request_signal(65),
1479	request(66) =>request_signal(66),
1480	request(67) =>request_signal(67),
1481	request(68) =>request_signal(68),
1482	request(69) =>request_signal(69),
1483	request(70) =>request_signal(70),
1484	request(71) =>request_signal(71),
1485	request(72) =>request_signal(72)
1486	);
1487
1488	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1489	GENERIC MAP(number_of_ports =>9)
1490	PORT MAP(
1491	data_in => Port9_in,
1492	data_in_en => data_in_en(9),
1493	reset => reset,
1494	clk =>clk,
1495	grant(73) => grant_signal(73),
1496	grant(74) => grant_signal(74),
1497	grant(75) => grant_signal(75),
1498	grant(76) => grant_signal(76),
1499	grant(77) => grant_signal(77),
1500	grant(78) => grant_signal(78),
1501	grant(79) => grant_signal(79),
1502	grant(80) => grant_signal(80),
1503	grant(81) => grant_signal(81),
1504	fifo_full =>fifo_in_full(9),
1505	priority_rotation => priority_rotation_signal(9),
1506	fifo_empty => fifo_in_empty(9),
1507	data_out =>crossbar_in_port9,
1508	data_out_pulse =>crossbar_in_pulse9,
1509	request(73) =>request_signal(73),
1510	request(74) =>request_signal(74),
1511	request(75) =>request_signal(75),
1512	request(76) =>request_signal(76),
1513	request(77) =>request_signal(77),
1514	request(78) =>request_signal(78),
1515	request(79) =>request_signal(79),
1516	request(80) =>request_signal(80),
1517	request(81) =>request_signal(81)
1518	);
1519
1520	end generate switch9x9;
1521
1522
1523	-- switch 10 ports
1524	switch10x10 : if number_of_ports = 10 generate
1525
1526	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1527	GENERIC MAP(number_of_ports =>10)
1528	PORT MAP(
1529	data_in => Port1_in,
1530	data_in_en => data_in_en(1),
1531	reset => reset,
1532	clk =>clk,
1533	grant(1) => grant_signal(1),
1534	grant(2) => grant_signal(2),
1535	grant(3) => grant_signal(3),
1536	grant(4) => grant_signal(4),
1537	grant(5) => grant_signal(5),
1538	grant(6) => grant_signal(6),
1539	grant(7) => grant_signal(7),
1540	grant(8) => grant_signal(8),
1541	grant(9) => grant_signal(9),
1542	grant(10) => grant_signal(10),
1543	fifo_full =>fifo_in_full(1),
1544	priority_rotation => priority_rotation_signal(1),
1545	fifo_empty => fifo_in_empty(1),
1546	data_out =>crossbar_in_port1,
1547	data_out_pulse =>crossbar_in_pulse1,
1548	request(1) =>request_signal(1),
1549	request(2) =>request_signal(2),
1550	request(3) =>request_signal(3),
1551	request(4) =>request_signal(4),
1552	request(5) =>request_signal(5),
1553	request(6) =>request_signal(6),
1554	request(7) =>request_signal(7),
1555	request(8) =>request_signal(8),
1556	request(9) =>request_signal(9),
1557	request(10) =>request_signal(10)
1558	);
1559
1560	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1561	GENERIC MAP(number_of_ports =>10)
1562	PORT MAP(
1563	data_in => Port2_in,
1564	data_in_en => data_in_en(2),
1565	reset => reset,
1566	clk =>clk,
1567	grant(11) => grant_signal(11),
1568	grant(12) => grant_signal(12),
1569	grant(13) => grant_signal(13),
1570	grant(14) => grant_signal(14),
1571	grant(15) => grant_signal(15),
1572	grant(16) => grant_signal(16),
1573	grant(17) => grant_signal(17),
1574	grant(18) => grant_signal(18),
1575	grant(19) => grant_signal(19),
1576	grant(20) => grant_signal(20),
1577	fifo_full =>fifo_in_full(2),
1578	priority_rotation => priority_rotation_signal(2),
1579	fifo_empty => fifo_in_empty(2),
1580	data_out =>crossbar_in_port2,
1581	data_out_pulse =>crossbar_in_pulse2,
1582	request(11) =>request_signal(11),
1583	request(12) =>request_signal(12),
1584	request(13) =>request_signal(13),
1585	request(14) =>request_signal(14),
1586	request(15) =>request_signal(15),
1587	request(16) =>request_signal(16),
1588	request(17) =>request_signal(17),
1589	request(18) =>request_signal(18),
1590	request(19) =>request_signal(19),
1591	request(20) =>request_signal(20)
1592	);
1593
1594	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1595	GENERIC MAP(number_of_ports =>10)
1596	PORT MAP(
1597	data_in => Port3_in,
1598	data_in_en => data_in_en(3),
1599	reset => reset,
1600	clk =>clk,
1601	grant(21) => grant_signal(21),
1602	grant(22) => grant_signal(22),
1603	grant(23) => grant_signal(23),
1604	grant(24) => grant_signal(24),
1605	grant(25) => grant_signal(25),
1606	grant(26) => grant_signal(26),
1607	grant(27) => grant_signal(27),
1608	grant(28) => grant_signal(28),
1609	grant(29) => grant_signal(29),
1610	grant(30) => grant_signal(30),
1611	fifo_full =>fifo_in_full(3),
1612	priority_rotation => priority_rotation_signal(3),
1613	fifo_empty => fifo_in_empty(3),
1614	data_out =>crossbar_in_port3,
1615	data_out_pulse =>crossbar_in_pulse3,
1616	request(21) =>request_signal(21),
1617	request(22) =>request_signal(22),
1618	request(23) =>request_signal(23),
1619	request(24) =>request_signal(24),
1620	request(25) =>request_signal(25),
1621	request(26) =>request_signal(26),
1622	request(27) =>request_signal(27),
1623	request(28) =>request_signal(28),
1624	request(29) =>request_signal(29),
1625	request(30) =>request_signal(30)
1626	);
1627
1628	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1629	GENERIC MAP(number_of_ports =>10)
1630	PORT MAP(
1631	data_in => Port4_in,
1632	data_in_en => data_in_en(4),
1633	reset => reset,
1634	clk =>clk,
1635	grant(31) => grant_signal(31),
1636	grant(32) => grant_signal(32),
1637	grant(33) => grant_signal(33),
1638	grant(34) => grant_signal(34),
1639	grant(35) => grant_signal(35),
1640	grant(36) => grant_signal(36),
1641	grant(37) => grant_signal(37),
1642	grant(38) => grant_signal(38),
1643	grant(39) => grant_signal(39),
1644	grant(40) => grant_signal(40),
1645	fifo_full =>fifo_in_full(4),
1646	priority_rotation => priority_rotation_signal(4),
1647	fifo_empty => fifo_in_empty(4),
1648	data_out =>crossbar_in_port4,
1649	data_out_pulse =>crossbar_in_pulse4,
1650	request(31) =>request_signal(31),
1651	request(32) =>request_signal(32),
1652	request(33) =>request_signal(33),
1653	request(34) =>request_signal(34),
1654	request(35) =>request_signal(35),
1655	request(36) =>request_signal(36),
1656	request(37) =>request_signal(37),
1657	request(38) =>request_signal(38),
1658	request(39) =>request_signal(39),
1659	request(40) =>request_signal(40)
1660	);
1661
1662	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1663	GENERIC MAP(number_of_ports =>10)
1664	PORT MAP(
1665	data_in => Port5_in,
1666	data_in_en => data_in_en(5),
1667	reset => reset,
1668	clk =>clk,
1669	grant(41) => grant_signal(41),
1670	grant(42) => grant_signal(42),
1671	grant(43) => grant_signal(43),
1672	grant(44) => grant_signal(44),
1673	grant(45) => grant_signal(45),
1674	grant(46) => grant_signal(46),
1675	grant(47) => grant_signal(47),
1676	grant(48) => grant_signal(48),
1677	grant(49) => grant_signal(49),
1678	grant(50) => grant_signal(50),
1679	fifo_full =>fifo_in_full(5),
1680	priority_rotation => priority_rotation_signal(5),
1681	fifo_empty => fifo_in_empty(5),
1682	data_out =>crossbar_in_port5,
1683	data_out_pulse =>crossbar_in_pulse5,
1684	request(41) =>request_signal(41),
1685	request(42) =>request_signal(42),
1686	request(43) =>request_signal(43),
1687	request(44) =>request_signal(44),
1688	request(45) =>request_signal(45),
1689	request(46) =>request_signal(46),
1690	request(47) =>request_signal(47),
1691	request(48) =>request_signal(48),
1692	request(49) =>request_signal(49),
1693	request(50) =>request_signal(50)
1694	);
1695
1696	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1697	GENERIC MAP(number_of_ports =>10)
1698	PORT MAP(
1699	data_in => Port6_in,
1700	data_in_en => data_in_en(6),
1701	reset => reset,
1702	clk =>clk,
1703	grant(51) => grant_signal(51),
1704	grant(52) => grant_signal(52),
1705	grant(53) => grant_signal(53),
1706	grant(54) => grant_signal(54),
1707	grant(55) => grant_signal(55),
1708	grant(56) => grant_signal(56),
1709	grant(57) => grant_signal(57),
1710	grant(58) => grant_signal(58),
1711	grant(59) => grant_signal(59),
1712	grant(60) => grant_signal(60),
1713	fifo_full =>fifo_in_full(6),
1714	priority_rotation => priority_rotation_signal(6),
1715	fifo_empty => fifo_in_empty(6),
1716	data_out =>crossbar_in_port6,
1717	data_out_pulse =>crossbar_in_pulse6,
1718	request(51) =>request_signal(51),
1719	request(52) =>request_signal(52),
1720	request(53) =>request_signal(53),
1721	request(54) =>request_signal(54),
1722	request(55) =>request_signal(55),
1723	request(56) =>request_signal(56),
1724	request(57) =>request_signal(57),
1725	request(58) =>request_signal(58),
1726	request(59) =>request_signal(59),
1727	request(60) =>request_signal(60)
1728	);
1729
1730	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1731	GENERIC MAP(number_of_ports =>10)
1732	PORT MAP(
1733	data_in => Port7_in,
1734	data_in_en => data_in_en(7),
1735	reset => reset,
1736	clk =>clk,
1737	grant(61) => grant_signal(61),
1738	grant(62) => grant_signal(62),
1739	grant(63) => grant_signal(63),
1740	grant(64) => grant_signal(64),
1741	grant(65) => grant_signal(65),
1742	grant(66) => grant_signal(66),
1743	grant(67) => grant_signal(67),
1744	grant(68) => grant_signal(68),
1745	grant(69) => grant_signal(69),
1746	grant(70) => grant_signal(70),
1747	fifo_full =>fifo_in_full(7),
1748	priority_rotation => priority_rotation_signal(7),
1749	fifo_empty => fifo_in_empty(7),
1750	data_out =>crossbar_in_port7,
1751	data_out_pulse =>crossbar_in_pulse7,
1752	request(61) =>request_signal(61),
1753	request(62) =>request_signal(62),
1754	request(63) =>request_signal(63),
1755	request(64) =>request_signal(64),
1756	request(65) =>request_signal(65),
1757	request(66) =>request_signal(66),
1758	request(67) =>request_signal(67),
1759	request(68) =>request_signal(68),
1760	request(69) =>request_signal(69),
1761	request(70) =>request_signal(70)
1762	);
1763
1764	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1765	GENERIC MAP(number_of_ports =>10)
1766	PORT MAP(
1767	data_in => Port8_in,
1768	data_in_en => data_in_en(8),
1769	reset => reset,
1770	clk =>clk,
1771	grant(71) => grant_signal(71),
1772	grant(72) => grant_signal(72),
1773	grant(73) => grant_signal(73),
1774	grant(74) => grant_signal(74),
1775	grant(75) => grant_signal(75),
1776	grant(76) => grant_signal(76),
1777	grant(77) => grant_signal(77),
1778	grant(78) => grant_signal(78),
1779	grant(79) => grant_signal(79),
1780	grant(80) => grant_signal(80),
1781	fifo_full =>fifo_in_full(8),
1782	priority_rotation => priority_rotation_signal(8),
1783	fifo_empty => fifo_in_empty(8),
1784	data_out =>crossbar_in_port8,
1785	data_out_pulse =>crossbar_in_pulse8,
1786	request(71) =>request_signal(71),
1787	request(72) =>request_signal(72),
1788	request(73) =>request_signal(73),
1789	request(74) =>request_signal(74),
1790	request(75) =>request_signal(75),
1791	request(76) =>request_signal(76),
1792	request(77) =>request_signal(77),
1793	request(78) =>request_signal(78),
1794	request(79) =>request_signal(79),
1795	request(80) =>request_signal(80)
1796	);
1797
1798	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1799	GENERIC MAP(number_of_ports =>10)
1800	PORT MAP(
1801	data_in => Port9_in,
1802	data_in_en => data_in_en(9),
1803	reset => reset,
1804	clk =>clk,
1805	grant(81) => grant_signal(81),
1806	grant(82) => grant_signal(82),
1807	grant(83) => grant_signal(83),
1808	grant(84) => grant_signal(84),
1809	grant(85) => grant_signal(85),
1810	grant(86) => grant_signal(86),
1811	grant(87) => grant_signal(87),
1812	grant(88) => grant_signal(88),
1813	grant(89) => grant_signal(89),
1814	grant(90) => grant_signal(90),
1815	fifo_full =>fifo_in_full(9),
1816	priority_rotation => priority_rotation_signal(9),
1817	fifo_empty => fifo_in_empty(9),
1818	data_out =>crossbar_in_port9,
1819	data_out_pulse =>crossbar_in_pulse9,
1820	request(81) =>request_signal(81),
1821	request(82) =>request_signal(82),
1822	request(83) =>request_signal(83),
1823	request(84) =>request_signal(84),
1824	request(85) =>request_signal(85),
1825	request(86) =>request_signal(86),
1826	request(87) =>request_signal(87),
1827	request(88) =>request_signal(88),
1828	request(89) =>request_signal(89),
1829	request(90) =>request_signal(90)
1830	);
1831
1832	PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1833	GENERIC MAP(number_of_ports =>10)
1834	PORT MAP(
1835	data_in => Port10_in,
1836	data_in_en => data_in_en(10),
1837	reset => reset,
1838	clk =>clk,
1839	grant(91) => grant_signal(91),
1840	grant(92) => grant_signal(92),
1841	grant(93) => grant_signal(93),
1842	grant(94) => grant_signal(94),
1843	grant(95) => grant_signal(95),
1844	grant(96) => grant_signal(96),
1845	grant(97) => grant_signal(97),
1846	grant(98) => grant_signal(98),
1847	grant(99) => grant_signal(99),
1848	grant(100) => grant_signal(100),
1849	fifo_full =>fifo_in_full(10),
1850	priority_rotation => priority_rotation_signal(10),
1851	fifo_empty => fifo_in_empty(10),
1852	data_out =>crossbar_in_port10,
1853	data_out_pulse =>crossbar_in_pulse10,
1854	request(91) =>request_signal(91),
1855	request(92) =>request_signal(92),
1856	request(93) =>request_signal(93),
1857	request(94) =>request_signal(94),
1858	request(95) =>request_signal(95),
1859	request(96) =>request_signal(96),
1860	request(97) =>request_signal(97),
1861	request(98) =>request_signal(98),
1862	request(99) =>request_signal(99),
1863	request(100) =>request_signal(100)
1864	);
1865
1866	end generate switch10x10;
1867
1868
1869	-- switch 11 ports
1870	switch11x11 : if number_of_ports = 11 generate
1871
1872	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1873	GENERIC MAP(number_of_ports =>11)
1874	PORT MAP(
1875	data_in => Port1_in,
1876	data_in_en => data_in_en(1),
1877	reset => reset,
1878	clk =>clk,
1879	grant(1) => grant_signal(1),
1880	grant(2) => grant_signal(2),
1881	grant(3) => grant_signal(3),
1882	grant(4) => grant_signal(4),
1883	grant(5) => grant_signal(5),
1884	grant(6) => grant_signal(6),
1885	grant(7) => grant_signal(7),
1886	grant(8) => grant_signal(8),
1887	grant(9) => grant_signal(9),
1888	grant(10) => grant_signal(10),
1889	grant(11) => grant_signal(11),
1890	fifo_full =>fifo_in_full(1),
1891	priority_rotation => priority_rotation_signal(1),
1892	fifo_empty => fifo_in_empty(1),
1893	data_out =>crossbar_in_port1,
1894	data_out_pulse =>crossbar_in_pulse1,
1895	request(1) =>request_signal(1),
1896	request(2) =>request_signal(2),
1897	request(3) =>request_signal(3),
1898	request(4) =>request_signal(4),
1899	request(5) =>request_signal(5),
1900	request(6) =>request_signal(6),
1901	request(7) =>request_signal(7),
1902	request(8) =>request_signal(8),
1903	request(9) =>request_signal(9),
1904	request(10) =>request_signal(10),
1905	request(11) =>request_signal(11)
1906	);
1907
1908	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1909	GENERIC MAP(number_of_ports =>11)
1910	PORT MAP(
1911	data_in => Port2_in,
1912	data_in_en => data_in_en(2),
1913	reset => reset,
1914	clk =>clk,
1915	grant(12) => grant_signal(12),
1916	grant(13) => grant_signal(13),
1917	grant(14) => grant_signal(14),
1918	grant(15) => grant_signal(15),
1919	grant(16) => grant_signal(16),
1920	grant(17) => grant_signal(17),
1921	grant(18) => grant_signal(18),
1922	grant(19) => grant_signal(19),
1923	grant(20) => grant_signal(20),
1924	grant(21) => grant_signal(21),
1925	grant(22) => grant_signal(22),
1926	fifo_full =>fifo_in_full(2),
1927	priority_rotation => priority_rotation_signal(2),
1928	fifo_empty => fifo_in_empty(2),
1929	data_out =>crossbar_in_port2,
1930	data_out_pulse =>crossbar_in_pulse2,
1931	request(12) =>request_signal(12),
1932	request(13) =>request_signal(13),
1933	request(14) =>request_signal(14),
1934	request(15) =>request_signal(15),
1935	request(16) =>request_signal(16),
1936	request(17) =>request_signal(17),
1937	request(18) =>request_signal(18),
1938	request(19) =>request_signal(19),
1939	request(20) =>request_signal(20),
1940	request(21) =>request_signal(21),
1941	request(22) =>request_signal(22)
1942	);
1943
1944	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1945	GENERIC MAP(number_of_ports =>11)
1946	PORT MAP(
1947	data_in => Port3_in,
1948	data_in_en => data_in_en(3),
1949	reset => reset,
1950	clk =>clk,
1951	grant(23) => grant_signal(23),
1952	grant(24) => grant_signal(24),
1953	grant(25) => grant_signal(25),
1954	grant(26) => grant_signal(26),
1955	grant(27) => grant_signal(27),
1956	grant(28) => grant_signal(28),
1957	grant(29) => grant_signal(29),
1958	grant(30) => grant_signal(30),
1959	grant(31) => grant_signal(31),
1960	grant(32) => grant_signal(32),
1961	grant(33) => grant_signal(33),
1962	fifo_full =>fifo_in_full(3),
1963	priority_rotation => priority_rotation_signal(3),
1964	fifo_empty => fifo_in_empty(3),
1965	data_out =>crossbar_in_port3,
1966	data_out_pulse =>crossbar_in_pulse3,
1967	request(23) =>request_signal(23),
1968	request(24) =>request_signal(24),
1969	request(25) =>request_signal(25),
1970	request(26) =>request_signal(26),
1971	request(27) =>request_signal(27),
1972	request(28) =>request_signal(28),
1973	request(29) =>request_signal(29),
1974	request(30) =>request_signal(30),
1975	request(31) =>request_signal(31),
1976	request(32) =>request_signal(32),
1977	request(33) =>request_signal(33)
1978	);
1979
1980	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
1981	GENERIC MAP(number_of_ports =>11)
1982	PORT MAP(
1983	data_in => Port4_in,
1984	data_in_en => data_in_en(4),
1985	reset => reset,
1986	clk =>clk,
1987	grant(34) => grant_signal(34),
1988	grant(35) => grant_signal(35),
1989	grant(36) => grant_signal(36),
1990	grant(37) => grant_signal(37),
1991	grant(38) => grant_signal(38),
1992	grant(39) => grant_signal(39),
1993	grant(40) => grant_signal(40),
1994	grant(41) => grant_signal(41),
1995	grant(42) => grant_signal(42),
1996	grant(43) => grant_signal(43),
1997	grant(44) => grant_signal(44),
1998	fifo_full =>fifo_in_full(4),
1999	priority_rotation => priority_rotation_signal(4),
2000	fifo_empty => fifo_in_empty(4),
2001	data_out =>crossbar_in_port4,
2002	data_out_pulse =>crossbar_in_pulse4,
2003	request(34) =>request_signal(34),
2004	request(35) =>request_signal(35),
2005	request(36) =>request_signal(36),
2006	request(37) =>request_signal(37),
2007	request(38) =>request_signal(38),
2008	request(39) =>request_signal(39),
2009	request(40) =>request_signal(40),
2010	request(41) =>request_signal(41),
2011	request(42) =>request_signal(42),
2012	request(43) =>request_signal(43),
2013	request(44) =>request_signal(44)
2014	);
2015
2016	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2017	GENERIC MAP(number_of_ports =>11)
2018	PORT MAP(
2019	data_in => Port5_in,
2020	data_in_en => data_in_en(5),
2021	reset => reset,
2022	clk =>clk,
2023	grant(45) => grant_signal(45),
2024	grant(46) => grant_signal(46),
2025	grant(47) => grant_signal(47),
2026	grant(48) => grant_signal(48),
2027	grant(49) => grant_signal(49),
2028	grant(50) => grant_signal(50),
2029	grant(51) => grant_signal(51),
2030	grant(52) => grant_signal(52),
2031	grant(53) => grant_signal(53),
2032	grant(54) => grant_signal(54),
2033	grant(55) => grant_signal(55),
2034	fifo_full =>fifo_in_full(5),
2035	priority_rotation => priority_rotation_signal(5),
2036	fifo_empty => fifo_in_empty(5),
2037	data_out =>crossbar_in_port5,
2038	data_out_pulse =>crossbar_in_pulse5,
2039	request(45) =>request_signal(45),
2040	request(46) =>request_signal(46),
2041	request(47) =>request_signal(47),
2042	request(48) =>request_signal(48),
2043	request(49) =>request_signal(49),
2044	request(50) =>request_signal(50),
2045	request(51) =>request_signal(51),
2046	request(52) =>request_signal(52),
2047	request(53) =>request_signal(53),
2048	request(54) =>request_signal(54),
2049	request(55) =>request_signal(55)
2050	);
2051
2052	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2053	GENERIC MAP(number_of_ports =>11)
2054	PORT MAP(
2055	data_in => Port6_in,
2056	data_in_en => data_in_en(6),
2057	reset => reset,
2058	clk =>clk,
2059	grant(56) => grant_signal(56),
2060	grant(57) => grant_signal(57),
2061	grant(58) => grant_signal(58),
2062	grant(59) => grant_signal(59),
2063	grant(60) => grant_signal(60),
2064	grant(61) => grant_signal(61),
2065	grant(62) => grant_signal(62),
2066	grant(63) => grant_signal(63),
2067	grant(64) => grant_signal(64),
2068	grant(65) => grant_signal(65),
2069	grant(66) => grant_signal(66),
2070	fifo_full =>fifo_in_full(6),
2071	priority_rotation => priority_rotation_signal(6),
2072	fifo_empty => fifo_in_empty(6),
2073	data_out =>crossbar_in_port6,
2074	data_out_pulse =>crossbar_in_pulse6,
2075	request(56) =>request_signal(56),
2076	request(57) =>request_signal(57),
2077	request(58) =>request_signal(58),
2078	request(59) =>request_signal(59),
2079	request(60) =>request_signal(60),
2080	request(61) =>request_signal(61),
2081	request(62) =>request_signal(62),
2082	request(63) =>request_signal(63),
2083	request(64) =>request_signal(64),
2084	request(65) =>request_signal(65),
2085	request(66) =>request_signal(66)
2086	);
2087
2088	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2089	GENERIC MAP(number_of_ports =>11)
2090	PORT MAP(
2091	data_in => Port7_in,
2092	data_in_en => data_in_en(7),
2093	reset => reset,
2094	clk =>clk,
2095	grant(67) => grant_signal(67),
2096	grant(68) => grant_signal(68),
2097	grant(69) => grant_signal(69),
2098	grant(70) => grant_signal(70),
2099	grant(71) => grant_signal(71),
2100	grant(72) => grant_signal(72),
2101	grant(73) => grant_signal(73),
2102	grant(74) => grant_signal(74),
2103	grant(75) => grant_signal(75),
2104	grant(76) => grant_signal(76),
2105	grant(77) => grant_signal(77),
2106	fifo_full =>fifo_in_full(7),
2107	priority_rotation => priority_rotation_signal(7),
2108	fifo_empty => fifo_in_empty(7),
2109	data_out =>crossbar_in_port7,
2110	data_out_pulse =>crossbar_in_pulse7,
2111	request(67) =>request_signal(67),
2112	request(68) =>request_signal(68),
2113	request(69) =>request_signal(69),
2114	request(70) =>request_signal(70),
2115	request(71) =>request_signal(71),
2116	request(72) =>request_signal(72),
2117	request(73) =>request_signal(73),
2118	request(74) =>request_signal(74),
2119	request(75) =>request_signal(75),
2120	request(76) =>request_signal(76),
2121	request(77) =>request_signal(77)
2122	);
2123
2124	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2125	GENERIC MAP(number_of_ports =>11)
2126	PORT MAP(
2127	data_in => Port8_in,
2128	data_in_en => data_in_en(8),
2129	reset => reset,
2130	clk =>clk,
2131	grant(78) => grant_signal(78),
2132	grant(79) => grant_signal(79),
2133	grant(80) => grant_signal(80),
2134	grant(81) => grant_signal(81),
2135	grant(82) => grant_signal(82),
2136	grant(83) => grant_signal(83),
2137	grant(84) => grant_signal(84),
2138	grant(85) => grant_signal(85),
2139	grant(86) => grant_signal(86),
2140	grant(87) => grant_signal(87),
2141	grant(88) => grant_signal(88),
2142	fifo_full =>fifo_in_full(8),
2143	priority_rotation => priority_rotation_signal(8),
2144	fifo_empty => fifo_in_empty(8),
2145	data_out =>crossbar_in_port8,
2146	data_out_pulse =>crossbar_in_pulse8,
2147	request(78) =>request_signal(78),
2148	request(79) =>request_signal(79),
2149	request(80) =>request_signal(80),
2150	request(81) =>request_signal(81),
2151	request(82) =>request_signal(82),
2152	request(83) =>request_signal(83),
2153	request(84) =>request_signal(84),
2154	request(85) =>request_signal(85),
2155	request(86) =>request_signal(86),
2156	request(87) =>request_signal(87),
2157	request(88) =>request_signal(88)
2158	);
2159
2160	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2161	GENERIC MAP(number_of_ports =>11)
2162	PORT MAP(
2163	data_in => Port9_in,
2164	data_in_en => data_in_en(9),
2165	reset => reset,
2166	clk =>clk,
2167	grant(89) => grant_signal(89),
2168	grant(90) => grant_signal(90),
2169	grant(91) => grant_signal(91),
2170	grant(92) => grant_signal(92),
2171	grant(93) => grant_signal(93),
2172	grant(94) => grant_signal(94),
2173	grant(95) => grant_signal(95),
2174	grant(96) => grant_signal(96),
2175	grant(97) => grant_signal(97),
2176	grant(98) => grant_signal(98),
2177	grant(99) => grant_signal(99),
2178	fifo_full =>fifo_in_full(9),
2179	priority_rotation => priority_rotation_signal(9),
2180	fifo_empty => fifo_in_empty(9),
2181	data_out =>crossbar_in_port9,
2182	data_out_pulse =>crossbar_in_pulse9,
2183	request(89) =>request_signal(89),
2184	request(90) =>request_signal(90),
2185	request(91) =>request_signal(91),
2186	request(92) =>request_signal(92),
2187	request(93) =>request_signal(93),
2188	request(94) =>request_signal(94),
2189	request(95) =>request_signal(95),
2190	request(96) =>request_signal(96),
2191	request(97) =>request_signal(97),
2192	request(98) =>request_signal(98),
2193	request(99) =>request_signal(99)
2194	);
2195
2196	PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2197	GENERIC MAP(number_of_ports =>11)
2198	PORT MAP(
2199	data_in => Port10_in,
2200	data_in_en => data_in_en(10),
2201	reset => reset,
2202	clk =>clk,
2203	grant(100) => grant_signal(100),
2204	grant(101) => grant_signal(101),
2205	grant(102) => grant_signal(102),
2206	grant(103) => grant_signal(103),
2207	grant(104) => grant_signal(104),
2208	grant(105) => grant_signal(105),
2209	grant(106) => grant_signal(106),
2210	grant(107) => grant_signal(107),
2211	grant(108) => grant_signal(108),
2212	grant(109) => grant_signal(109),
2213	grant(110) => grant_signal(110),
2214	fifo_full =>fifo_in_full(10),
2215	priority_rotation => priority_rotation_signal(10),
2216	fifo_empty => fifo_in_empty(10),
2217	data_out =>crossbar_in_port10,
2218	data_out_pulse =>crossbar_in_pulse10,
2219	request(100) =>request_signal(100),
2220	request(101) =>request_signal(101),
2221	request(102) =>request_signal(102),
2222	request(103) =>request_signal(103),
2223	request(104) =>request_signal(104),
2224	request(105) =>request_signal(105),
2225	request(106) =>request_signal(106),
2226	request(107) =>request_signal(107),
2227	request(108) =>request_signal(108),
2228	request(109) =>request_signal(109),
2229	request(110) =>request_signal(110)
2230	);
2231
2232	PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2233	GENERIC MAP(number_of_ports =>11)
2234	PORT MAP(
2235	data_in => Port11_in,
2236	data_in_en => data_in_en(11),
2237	reset => reset,
2238	clk =>clk,
2239	grant(111) => grant_signal(111),
2240	grant(112) => grant_signal(112),
2241	grant(113) => grant_signal(113),
2242	grant(114) => grant_signal(114),
2243	grant(115) => grant_signal(115),
2244	grant(116) => grant_signal(116),
2245	grant(117) => grant_signal(117),
2246	grant(118) => grant_signal(118),
2247	grant(119) => grant_signal(119),
2248	grant(120) => grant_signal(120),
2249	grant(121) => grant_signal(121),
2250	fifo_full =>fifo_in_full(11),
2251	priority_rotation => priority_rotation_signal(11),
2252	fifo_empty => fifo_in_empty(11),
2253	data_out =>crossbar_in_port11,
2254	data_out_pulse =>crossbar_in_pulse11,
2255	request(111) =>request_signal(111),
2256	request(112) =>request_signal(112),
2257	request(113) =>request_signal(113),
2258	request(114) =>request_signal(114),
2259	request(115) =>request_signal(115),
2260	request(116) =>request_signal(116),
2261	request(117) =>request_signal(117),
2262	request(118) =>request_signal(118),
2263	request(119) =>request_signal(119),
2264	request(120) =>request_signal(120),
2265	request(121) =>request_signal(121)
2266	);
2267
2268	end generate switch11x11;
2269
2270
2271	-- switch 12 ports
2272	switch12x12 : if number_of_ports = 12 generate
2273
2274	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2275	GENERIC MAP(number_of_ports =>12)
2276	PORT MAP(
2277	data_in => Port1_in,
2278	data_in_en => data_in_en(1),
2279	reset => reset,
2280	clk =>clk,
2281	grant(1) => grant_signal(1),
2282	grant(2) => grant_signal(2),
2283	grant(3) => grant_signal(3),
2284	grant(4) => grant_signal(4),
2285	grant(5) => grant_signal(5),
2286	grant(6) => grant_signal(6),
2287	grant(7) => grant_signal(7),
2288	grant(8) => grant_signal(8),
2289	grant(9) => grant_signal(9),
2290	grant(10) => grant_signal(10),
2291	grant(11) => grant_signal(11),
2292	grant(12) => grant_signal(12),
2293	fifo_full =>fifo_in_full(1),
2294	priority_rotation => priority_rotation_signal(1),
2295	fifo_empty => fifo_in_empty(1),
2296	data_out =>crossbar_in_port1,
2297	data_out_pulse =>crossbar_in_pulse1,
2298	request(1) =>request_signal(1),
2299	request(2) =>request_signal(2),
2300	request(3) =>request_signal(3),
2301	request(4) =>request_signal(4),
2302	request(5) =>request_signal(5),
2303	request(6) =>request_signal(6),
2304	request(7) =>request_signal(7),
2305	request(8) =>request_signal(8),
2306	request(9) =>request_signal(9),
2307	request(10) =>request_signal(10),
2308	request(11) =>request_signal(11),
2309	request(12) =>request_signal(12)
2310	);
2311
2312	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2313	GENERIC MAP(number_of_ports =>12)
2314	PORT MAP(
2315	data_in => Port2_in,
2316	data_in_en => data_in_en(2),
2317	reset => reset,
2318	clk =>clk,
2319	grant(13) => grant_signal(13),
2320	grant(14) => grant_signal(14),
2321	grant(15) => grant_signal(15),
2322	grant(16) => grant_signal(16),
2323	grant(17) => grant_signal(17),
2324	grant(18) => grant_signal(18),
2325	grant(19) => grant_signal(19),
2326	grant(20) => grant_signal(20),
2327	grant(21) => grant_signal(21),
2328	grant(22) => grant_signal(22),
2329	grant(23) => grant_signal(23),
2330	grant(24) => grant_signal(24),
2331	fifo_full =>fifo_in_full(2),
2332	priority_rotation => priority_rotation_signal(2),
2333	fifo_empty => fifo_in_empty(2),
2334	data_out =>crossbar_in_port2,
2335	data_out_pulse =>crossbar_in_pulse2,
2336	request(13) =>request_signal(13),
2337	request(14) =>request_signal(14),
2338	request(15) =>request_signal(15),
2339	request(16) =>request_signal(16),
2340	request(17) =>request_signal(17),
2341	request(18) =>request_signal(18),
2342	request(19) =>request_signal(19),
2343	request(20) =>request_signal(20),
2344	request(21) =>request_signal(21),
2345	request(22) =>request_signal(22),
2346	request(23) =>request_signal(23),
2347	request(24) =>request_signal(24)
2348	);
2349
2350	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2351	GENERIC MAP(number_of_ports =>12)
2352	PORT MAP(
2353	data_in => Port3_in,
2354	data_in_en => data_in_en(3),
2355	reset => reset,
2356	clk =>clk,
2357	grant(25) => grant_signal(25),
2358	grant(26) => grant_signal(26),
2359	grant(27) => grant_signal(27),
2360	grant(28) => grant_signal(28),
2361	grant(29) => grant_signal(29),
2362	grant(30) => grant_signal(30),
2363	grant(31) => grant_signal(31),
2364	grant(32) => grant_signal(32),
2365	grant(33) => grant_signal(33),
2366	grant(34) => grant_signal(34),
2367	grant(35) => grant_signal(35),
2368	grant(36) => grant_signal(36),
2369	fifo_full =>fifo_in_full(3),
2370	priority_rotation => priority_rotation_signal(3),
2371	fifo_empty => fifo_in_empty(3),
2372	data_out =>crossbar_in_port3,
2373	data_out_pulse =>crossbar_in_pulse3,
2374	request(25) =>request_signal(25),
2375	request(26) =>request_signal(26),
2376	request(27) =>request_signal(27),
2377	request(28) =>request_signal(28),
2378	request(29) =>request_signal(29),
2379	request(30) =>request_signal(30),
2380	request(31) =>request_signal(31),
2381	request(32) =>request_signal(32),
2382	request(33) =>request_signal(33),
2383	request(34) =>request_signal(34),
2384	request(35) =>request_signal(35),
2385	request(36) =>request_signal(36)
2386	);
2387
2388	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2389	GENERIC MAP(number_of_ports =>12)
2390	PORT MAP(
2391	data_in => Port4_in,
2392	data_in_en => data_in_en(4),
2393	reset => reset,
2394	clk =>clk,
2395	grant(37) => grant_signal(37),
2396	grant(38) => grant_signal(38),
2397	grant(39) => grant_signal(39),
2398	grant(40) => grant_signal(40),
2399	grant(41) => grant_signal(41),
2400	grant(42) => grant_signal(42),
2401	grant(43) => grant_signal(43),
2402	grant(44) => grant_signal(44),
2403	grant(45) => grant_signal(45),
2404	grant(46) => grant_signal(46),
2405	grant(47) => grant_signal(47),
2406	grant(48) => grant_signal(48),
2407	fifo_full =>fifo_in_full(4),
2408	priority_rotation => priority_rotation_signal(4),
2409	fifo_empty => fifo_in_empty(4),
2410	data_out =>crossbar_in_port4,
2411	data_out_pulse =>crossbar_in_pulse4,
2412	request(37) =>request_signal(37),
2413	request(38) =>request_signal(38),
2414	request(39) =>request_signal(39),
2415	request(40) =>request_signal(40),
2416	request(41) =>request_signal(41),
2417	request(42) =>request_signal(42),
2418	request(43) =>request_signal(43),
2419	request(44) =>request_signal(44),
2420	request(45) =>request_signal(45),
2421	request(46) =>request_signal(46),
2422	request(47) =>request_signal(47),
2423	request(48) =>request_signal(48)
2424	);
2425
2426	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2427	GENERIC MAP(number_of_ports =>12)
2428	PORT MAP(
2429	data_in => Port5_in,
2430	data_in_en => data_in_en(5),
2431	reset => reset,
2432	clk =>clk,
2433	grant(49) => grant_signal(49),
2434	grant(50) => grant_signal(50),
2435	grant(51) => grant_signal(51),
2436	grant(52) => grant_signal(52),
2437	grant(53) => grant_signal(53),
2438	grant(54) => grant_signal(54),
2439	grant(55) => grant_signal(55),
2440	grant(56) => grant_signal(56),
2441	grant(57) => grant_signal(57),
2442	grant(58) => grant_signal(58),
2443	grant(59) => grant_signal(59),
2444	grant(60) => grant_signal(60),
2445	fifo_full =>fifo_in_full(5),
2446	priority_rotation => priority_rotation_signal(5),
2447	fifo_empty => fifo_in_empty(5),
2448	data_out =>crossbar_in_port5,
2449	data_out_pulse =>crossbar_in_pulse5,
2450	request(49) =>request_signal(49),
2451	request(50) =>request_signal(50),
2452	request(51) =>request_signal(51),
2453	request(52) =>request_signal(52),
2454	request(53) =>request_signal(53),
2455	request(54) =>request_signal(54),
2456	request(55) =>request_signal(55),
2457	request(56) =>request_signal(56),
2458	request(57) =>request_signal(57),
2459	request(58) =>request_signal(58),
2460	request(59) =>request_signal(59),
2461	request(60) =>request_signal(60)
2462	);
2463
2464	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2465	GENERIC MAP(number_of_ports =>12)
2466	PORT MAP(
2467	data_in => Port6_in,
2468	data_in_en => data_in_en(6),
2469	reset => reset,
2470	clk =>clk,
2471	grant(61) => grant_signal(61),
2472	grant(62) => grant_signal(62),
2473	grant(63) => grant_signal(63),
2474	grant(64) => grant_signal(64),
2475	grant(65) => grant_signal(65),
2476	grant(66) => grant_signal(66),
2477	grant(67) => grant_signal(67),
2478	grant(68) => grant_signal(68),
2479	grant(69) => grant_signal(69),
2480	grant(70) => grant_signal(70),
2481	grant(71) => grant_signal(71),
2482	grant(72) => grant_signal(72),
2483	fifo_full =>fifo_in_full(6),
2484	priority_rotation => priority_rotation_signal(6),
2485	fifo_empty => fifo_in_empty(6),
2486	data_out =>crossbar_in_port6,
2487	data_out_pulse =>crossbar_in_pulse6,
2488	request(61) =>request_signal(61),
2489	request(62) =>request_signal(62),
2490	request(63) =>request_signal(63),
2491	request(64) =>request_signal(64),
2492	request(65) =>request_signal(65),
2493	request(66) =>request_signal(66),
2494	request(67) =>request_signal(67),
2495	request(68) =>request_signal(68),
2496	request(69) =>request_signal(69),
2497	request(70) =>request_signal(70),
2498	request(71) =>request_signal(71),
2499	request(72) =>request_signal(72)
2500	);
2501
2502	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2503	GENERIC MAP(number_of_ports =>12)
2504	PORT MAP(
2505	data_in => Port7_in,
2506	data_in_en => data_in_en(7),
2507	reset => reset,
2508	clk =>clk,
2509	grant(73) => grant_signal(73),
2510	grant(74) => grant_signal(74),
2511	grant(75) => grant_signal(75),
2512	grant(76) => grant_signal(76),
2513	grant(77) => grant_signal(77),
2514	grant(78) => grant_signal(78),
2515	grant(79) => grant_signal(79),
2516	grant(80) => grant_signal(80),
2517	grant(81) => grant_signal(81),
2518	grant(82) => grant_signal(82),
2519	grant(83) => grant_signal(83),
2520	grant(84) => grant_signal(84),
2521	fifo_full =>fifo_in_full(7),
2522	priority_rotation => priority_rotation_signal(7),
2523	fifo_empty => fifo_in_empty(7),
2524	data_out =>crossbar_in_port7,
2525	data_out_pulse =>crossbar_in_pulse7,
2526	request(73) =>request_signal(73),
2527	request(74) =>request_signal(74),
2528	request(75) =>request_signal(75),
2529	request(76) =>request_signal(76),
2530	request(77) =>request_signal(77),
2531	request(78) =>request_signal(78),
2532	request(79) =>request_signal(79),
2533	request(80) =>request_signal(80),
2534	request(81) =>request_signal(81),
2535	request(82) =>request_signal(82),
2536	request(83) =>request_signal(83),
2537	request(84) =>request_signal(84)
2538	);
2539
2540	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2541	GENERIC MAP(number_of_ports =>12)
2542	PORT MAP(
2543	data_in => Port8_in,
2544	data_in_en => data_in_en(8),
2545	reset => reset,
2546	clk =>clk,
2547	grant(85) => grant_signal(85),
2548	grant(86) => grant_signal(86),
2549	grant(87) => grant_signal(87),
2550	grant(88) => grant_signal(88),
2551	grant(89) => grant_signal(89),
2552	grant(90) => grant_signal(90),
2553	grant(91) => grant_signal(91),
2554	grant(92) => grant_signal(92),
2555	grant(93) => grant_signal(93),
2556	grant(94) => grant_signal(94),
2557	grant(95) => grant_signal(95),
2558	grant(96) => grant_signal(96),
2559	fifo_full =>fifo_in_full(8),
2560	priority_rotation => priority_rotation_signal(8),
2561	fifo_empty => fifo_in_empty(8),
2562	data_out =>crossbar_in_port8,
2563	data_out_pulse =>crossbar_in_pulse8,
2564	request(85) =>request_signal(85),
2565	request(86) =>request_signal(86),
2566	request(87) =>request_signal(87),
2567	request(88) =>request_signal(88),
2568	request(89) =>request_signal(89),
2569	request(90) =>request_signal(90),
2570	request(91) =>request_signal(91),
2571	request(92) =>request_signal(92),
2572	request(93) =>request_signal(93),
2573	request(94) =>request_signal(94),
2574	request(95) =>request_signal(95),
2575	request(96) =>request_signal(96)
2576	);
2577
2578	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2579	GENERIC MAP(number_of_ports =>12)
2580	PORT MAP(
2581	data_in => Port9_in,
2582	data_in_en => data_in_en(9),
2583	reset => reset,
2584	clk =>clk,
2585	grant(97) => grant_signal(97),
2586	grant(98) => grant_signal(98),
2587	grant(99) => grant_signal(99),
2588	grant(100) => grant_signal(100),
2589	grant(101) => grant_signal(101),
2590	grant(102) => grant_signal(102),
2591	grant(103) => grant_signal(103),
2592	grant(104) => grant_signal(104),
2593	grant(105) => grant_signal(105),
2594	grant(106) => grant_signal(106),
2595	grant(107) => grant_signal(107),
2596	grant(108) => grant_signal(108),
2597	fifo_full =>fifo_in_full(9),
2598	priority_rotation => priority_rotation_signal(9),
2599	fifo_empty => fifo_in_empty(9),
2600	data_out =>crossbar_in_port9,
2601	data_out_pulse =>crossbar_in_pulse9,
2602	request(97) =>request_signal(97),
2603	request(98) =>request_signal(98),
2604	request(99) =>request_signal(99),
2605	request(100) =>request_signal(100),
2606	request(101) =>request_signal(101),
2607	request(102) =>request_signal(102),
2608	request(103) =>request_signal(103),
2609	request(104) =>request_signal(104),
2610	request(105) =>request_signal(105),
2611	request(106) =>request_signal(106),
2612	request(107) =>request_signal(107),
2613	request(108) =>request_signal(108)
2614	);
2615
2616	PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2617	GENERIC MAP(number_of_ports =>12)
2618	PORT MAP(
2619	data_in => Port10_in,
2620	data_in_en => data_in_en(10),
2621	reset => reset,
2622	clk =>clk,
2623	grant(109) => grant_signal(109),
2624	grant(110) => grant_signal(110),
2625	grant(111) => grant_signal(111),
2626	grant(112) => grant_signal(112),
2627	grant(113) => grant_signal(113),
2628	grant(114) => grant_signal(114),
2629	grant(115) => grant_signal(115),
2630	grant(116) => grant_signal(116),
2631	grant(117) => grant_signal(117),
2632	grant(118) => grant_signal(118),
2633	grant(119) => grant_signal(119),
2634	grant(120) => grant_signal(120),
2635	fifo_full =>fifo_in_full(10),
2636	priority_rotation => priority_rotation_signal(10),
2637	fifo_empty => fifo_in_empty(10),
2638	data_out =>crossbar_in_port10,
2639	data_out_pulse =>crossbar_in_pulse10,
2640	request(109) =>request_signal(109),
2641	request(110) =>request_signal(110),
2642	request(111) =>request_signal(111),
2643	request(112) =>request_signal(112),
2644	request(113) =>request_signal(113),
2645	request(114) =>request_signal(114),
2646	request(115) =>request_signal(115),
2647	request(116) =>request_signal(116),
2648	request(117) =>request_signal(117),
2649	request(118) =>request_signal(118),
2650	request(119) =>request_signal(119),
2651	request(120) =>request_signal(120)
2652	);
2653
2654	PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2655	GENERIC MAP(number_of_ports =>12)
2656	PORT MAP(
2657	data_in => Port11_in,
2658	data_in_en => data_in_en(11),
2659	reset => reset,
2660	clk =>clk,
2661	grant(121) => grant_signal(121),
2662	grant(122) => grant_signal(122),
2663	grant(123) => grant_signal(123),
2664	grant(124) => grant_signal(124),
2665	grant(125) => grant_signal(125),
2666	grant(126) => grant_signal(126),
2667	grant(127) => grant_signal(127),
2668	grant(128) => grant_signal(128),
2669	grant(129) => grant_signal(129),
2670	grant(130) => grant_signal(130),
2671	grant(131) => grant_signal(131),
2672	grant(132) => grant_signal(132),
2673	fifo_full =>fifo_in_full(11),
2674	priority_rotation => priority_rotation_signal(11),
2675	fifo_empty => fifo_in_empty(11),
2676	data_out =>crossbar_in_port11,
2677	data_out_pulse =>crossbar_in_pulse11,
2678	request(121) =>request_signal(121),
2679	request(122) =>request_signal(122),
2680	request(123) =>request_signal(123),
2681	request(124) =>request_signal(124),
2682	request(125) =>request_signal(125),
2683	request(126) =>request_signal(126),
2684	request(127) =>request_signal(127),
2685	request(128) =>request_signal(128),
2686	request(129) =>request_signal(129),
2687	request(130) =>request_signal(130),
2688	request(131) =>request_signal(131),
2689	request(132) =>request_signal(132)
2690	);
2691
2692	PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2693	GENERIC MAP(number_of_ports =>12)
2694	PORT MAP(
2695	data_in => Port12_in,
2696	data_in_en => data_in_en(12),
2697	reset => reset,
2698	clk =>clk,
2699	grant(133) => grant_signal(133),
2700	grant(134) => grant_signal(134),
2701	grant(135) => grant_signal(135),
2702	grant(136) => grant_signal(136),
2703	grant(137) => grant_signal(137),
2704	grant(138) => grant_signal(138),
2705	grant(139) => grant_signal(139),
2706	grant(140) => grant_signal(140),
2707	grant(141) => grant_signal(141),
2708	grant(142) => grant_signal(142),
2709	grant(143) => grant_signal(143),
2710	grant(144) => grant_signal(144),
2711	fifo_full =>fifo_in_full(12),
2712	priority_rotation => priority_rotation_signal(12),
2713	fifo_empty => fifo_in_empty(12),
2714	data_out =>crossbar_in_port12,
2715	data_out_pulse =>crossbar_in_pulse12,
2716	request(133) =>request_signal(133),
2717	request(134) =>request_signal(134),
2718	request(135) =>request_signal(135),
2719	request(136) =>request_signal(136),
2720	request(137) =>request_signal(137),
2721	request(138) =>request_signal(138),
2722	request(139) =>request_signal(139),
2723	request(140) =>request_signal(140),
2724	request(141) =>request_signal(141),
2725	request(142) =>request_signal(142),
2726	request(143) =>request_signal(143),
2727	request(144) =>request_signal(144)
2728	);
2729
2730	end generate switch12x12;
2731
2732
2733	-- switch 13 ports
2734	switch13x13 : if number_of_ports = 13 generate
2735
2736	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2737	GENERIC MAP(number_of_ports =>13)
2738	PORT MAP(
2739	data_in => Port1_in,
2740	data_in_en => data_in_en(1),
2741	reset => reset,
2742	clk =>clk,
2743	grant(1) => grant_signal(1),
2744	grant(2) => grant_signal(2),
2745	grant(3) => grant_signal(3),
2746	grant(4) => grant_signal(4),
2747	grant(5) => grant_signal(5),
2748	grant(6) => grant_signal(6),
2749	grant(7) => grant_signal(7),
2750	grant(8) => grant_signal(8),
2751	grant(9) => grant_signal(9),
2752	grant(10) => grant_signal(10),
2753	grant(11) => grant_signal(11),
2754	grant(12) => grant_signal(12),
2755	grant(13) => grant_signal(13),
2756	fifo_full =>fifo_in_full(1),
2757	priority_rotation => priority_rotation_signal(1),
2758	fifo_empty => fifo_in_empty(1),
2759	data_out =>crossbar_in_port1,
2760	data_out_pulse =>crossbar_in_pulse1,
2761	request(1) =>request_signal(1),
2762	request(2) =>request_signal(2),
2763	request(3) =>request_signal(3),
2764	request(4) =>request_signal(4),
2765	request(5) =>request_signal(5),
2766	request(6) =>request_signal(6),
2767	request(7) =>request_signal(7),
2768	request(8) =>request_signal(8),
2769	request(9) =>request_signal(9),
2770	request(10) =>request_signal(10),
2771	request(11) =>request_signal(11),
2772	request(12) =>request_signal(12),
2773	request(13) =>request_signal(13)
2774	);
2775
2776	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2777	GENERIC MAP(number_of_ports =>13)
2778	PORT MAP(
2779	data_in => Port2_in,
2780	data_in_en => data_in_en(2),
2781	reset => reset,
2782	clk =>clk,
2783	grant(14) => grant_signal(14),
2784	grant(15) => grant_signal(15),
2785	grant(16) => grant_signal(16),
2786	grant(17) => grant_signal(17),
2787	grant(18) => grant_signal(18),
2788	grant(19) => grant_signal(19),
2789	grant(20) => grant_signal(20),
2790	grant(21) => grant_signal(21),
2791	grant(22) => grant_signal(22),
2792	grant(23) => grant_signal(23),
2793	grant(24) => grant_signal(24),
2794	grant(25) => grant_signal(25),
2795	grant(26) => grant_signal(26),
2796	fifo_full =>fifo_in_full(2),
2797	priority_rotation => priority_rotation_signal(2),
2798	fifo_empty => fifo_in_empty(2),
2799	data_out =>crossbar_in_port2,
2800	data_out_pulse =>crossbar_in_pulse2,
2801	request(14) =>request_signal(14),
2802	request(15) =>request_signal(15),
2803	request(16) =>request_signal(16),
2804	request(17) =>request_signal(17),
2805	request(18) =>request_signal(18),
2806	request(19) =>request_signal(19),
2807	request(20) =>request_signal(20),
2808	request(21) =>request_signal(21),
2809	request(22) =>request_signal(22),
2810	request(23) =>request_signal(23),
2811	request(24) =>request_signal(24),
2812	request(25) =>request_signal(25),
2813	request(26) =>request_signal(26)
2814	);
2815
2816	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2817	GENERIC MAP(number_of_ports =>13)
2818	PORT MAP(
2819	data_in => Port3_in,
2820	data_in_en => data_in_en(3),
2821	reset => reset,
2822	clk =>clk,
2823	grant(27) => grant_signal(27),
2824	grant(28) => grant_signal(28),
2825	grant(29) => grant_signal(29),
2826	grant(30) => grant_signal(30),
2827	grant(31) => grant_signal(31),
2828	grant(32) => grant_signal(32),
2829	grant(33) => grant_signal(33),
2830	grant(34) => grant_signal(34),
2831	grant(35) => grant_signal(35),
2832	grant(36) => grant_signal(36),
2833	grant(37) => grant_signal(37),
2834	grant(38) => grant_signal(38),
2835	grant(39) => grant_signal(39),
2836	fifo_full =>fifo_in_full(3),
2837	priority_rotation => priority_rotation_signal(3),
2838	fifo_empty => fifo_in_empty(3),
2839	data_out =>crossbar_in_port3,
2840	data_out_pulse =>crossbar_in_pulse3,
2841	request(27) =>request_signal(27),
2842	request(28) =>request_signal(28),
2843	request(29) =>request_signal(29),
2844	request(30) =>request_signal(30),
2845	request(31) =>request_signal(31),
2846	request(32) =>request_signal(32),
2847	request(33) =>request_signal(33),
2848	request(34) =>request_signal(34),
2849	request(35) =>request_signal(35),
2850	request(36) =>request_signal(36),
2851	request(37) =>request_signal(37),
2852	request(38) =>request_signal(38),
2853	request(39) =>request_signal(39)
2854	);
2855
2856	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2857	GENERIC MAP(number_of_ports =>13)
2858	PORT MAP(
2859	data_in => Port4_in,
2860	data_in_en => data_in_en(4),
2861	reset => reset,
2862	clk =>clk,
2863	grant(40) => grant_signal(40),
2864	grant(41) => grant_signal(41),
2865	grant(42) => grant_signal(42),
2866	grant(43) => grant_signal(43),
2867	grant(44) => grant_signal(44),
2868	grant(45) => grant_signal(45),
2869	grant(46) => grant_signal(46),
2870	grant(47) => grant_signal(47),
2871	grant(48) => grant_signal(48),
2872	grant(49) => grant_signal(49),
2873	grant(50) => grant_signal(50),
2874	grant(51) => grant_signal(51),
2875	grant(52) => grant_signal(52),
2876	fifo_full =>fifo_in_full(4),
2877	priority_rotation => priority_rotation_signal(4),
2878	fifo_empty => fifo_in_empty(4),
2879	data_out =>crossbar_in_port4,
2880	data_out_pulse =>crossbar_in_pulse4,
2881	request(40) =>request_signal(40),
2882	request(41) =>request_signal(41),
2883	request(42) =>request_signal(42),
2884	request(43) =>request_signal(43),
2885	request(44) =>request_signal(44),
2886	request(45) =>request_signal(45),
2887	request(46) =>request_signal(46),
2888	request(47) =>request_signal(47),
2889	request(48) =>request_signal(48),
2890	request(49) =>request_signal(49),
2891	request(50) =>request_signal(50),
2892	request(51) =>request_signal(51),
2893	request(52) =>request_signal(52)
2894	);
2895
2896	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2897	GENERIC MAP(number_of_ports =>13)
2898	PORT MAP(
2899	data_in => Port5_in,
2900	data_in_en => data_in_en(5),
2901	reset => reset,
2902	clk =>clk,
2903	grant(53) => grant_signal(53),
2904	grant(54) => grant_signal(54),
2905	grant(55) => grant_signal(55),
2906	grant(56) => grant_signal(56),
2907	grant(57) => grant_signal(57),
2908	grant(58) => grant_signal(58),
2909	grant(59) => grant_signal(59),
2910	grant(60) => grant_signal(60),
2911	grant(61) => grant_signal(61),
2912	grant(62) => grant_signal(62),
2913	grant(63) => grant_signal(63),
2914	grant(64) => grant_signal(64),
2915	grant(65) => grant_signal(65),
2916	fifo_full =>fifo_in_full(5),
2917	priority_rotation => priority_rotation_signal(5),
2918	fifo_empty => fifo_in_empty(5),
2919	data_out =>crossbar_in_port5,
2920	data_out_pulse =>crossbar_in_pulse5,
2921	request(53) =>request_signal(53),
2922	request(54) =>request_signal(54),
2923	request(55) =>request_signal(55),
2924	request(56) =>request_signal(56),
2925	request(57) =>request_signal(57),
2926	request(58) =>request_signal(58),
2927	request(59) =>request_signal(59),
2928	request(60) =>request_signal(60),
2929	request(61) =>request_signal(61),
2930	request(62) =>request_signal(62),
2931	request(63) =>request_signal(63),
2932	request(64) =>request_signal(64),
2933	request(65) =>request_signal(65)
2934	);
2935
2936	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2937	GENERIC MAP(number_of_ports =>13)
2938	PORT MAP(
2939	data_in => Port6_in,
2940	data_in_en => data_in_en(6),
2941	reset => reset,
2942	clk =>clk,
2943	grant(66) => grant_signal(66),
2944	grant(67) => grant_signal(67),
2945	grant(68) => grant_signal(68),
2946	grant(69) => grant_signal(69),
2947	grant(70) => grant_signal(70),
2948	grant(71) => grant_signal(71),
2949	grant(72) => grant_signal(72),
2950	grant(73) => grant_signal(73),
2951	grant(74) => grant_signal(74),
2952	grant(75) => grant_signal(75),
2953	grant(76) => grant_signal(76),
2954	grant(77) => grant_signal(77),
2955	grant(78) => grant_signal(78),
2956	fifo_full =>fifo_in_full(6),
2957	priority_rotation => priority_rotation_signal(6),
2958	fifo_empty => fifo_in_empty(6),
2959	data_out =>crossbar_in_port6,
2960	data_out_pulse =>crossbar_in_pulse6,
2961	request(66) =>request_signal(66),
2962	request(67) =>request_signal(67),
2963	request(68) =>request_signal(68),
2964	request(69) =>request_signal(69),
2965	request(70) =>request_signal(70),
2966	request(71) =>request_signal(71),
2967	request(72) =>request_signal(72),
2968	request(73) =>request_signal(73),
2969	request(74) =>request_signal(74),
2970	request(75) =>request_signal(75),
2971	request(76) =>request_signal(76),
2972	request(77) =>request_signal(77),
2973	request(78) =>request_signal(78)
2974	);
2975
2976	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
2977	GENERIC MAP(number_of_ports =>13)
2978	PORT MAP(
2979	data_in => Port7_in,
2980	data_in_en => data_in_en(7),
2981	reset => reset,
2982	clk =>clk,
2983	grant(79) => grant_signal(79),
2984	grant(80) => grant_signal(80),
2985	grant(81) => grant_signal(81),
2986	grant(82) => grant_signal(82),
2987	grant(83) => grant_signal(83),
2988	grant(84) => grant_signal(84),
2989	grant(85) => grant_signal(85),
2990	grant(86) => grant_signal(86),
2991	grant(87) => grant_signal(87),
2992	grant(88) => grant_signal(88),
2993	grant(89) => grant_signal(89),
2994	grant(90) => grant_signal(90),
2995	grant(91) => grant_signal(91),
2996	fifo_full =>fifo_in_full(7),
2997	priority_rotation => priority_rotation_signal(7),
2998	fifo_empty => fifo_in_empty(7),
2999	data_out =>crossbar_in_port7,
3000	data_out_pulse =>crossbar_in_pulse7,
3001	request(79) =>request_signal(79),
3002	request(80) =>request_signal(80),
3003	request(81) =>request_signal(81),
3004	request(82) =>request_signal(82),
3005	request(83) =>request_signal(83),
3006	request(84) =>request_signal(84),
3007	request(85) =>request_signal(85),
3008	request(86) =>request_signal(86),
3009	request(87) =>request_signal(87),
3010	request(88) =>request_signal(88),
3011	request(89) =>request_signal(89),
3012	request(90) =>request_signal(90),
3013	request(91) =>request_signal(91)
3014	);
3015
3016	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3017	GENERIC MAP(number_of_ports =>13)
3018	PORT MAP(
3019	data_in => Port8_in,
3020	data_in_en => data_in_en(8),
3021	reset => reset,
3022	clk =>clk,
3023	grant(92) => grant_signal(92),
3024	grant(93) => grant_signal(93),
3025	grant(94) => grant_signal(94),
3026	grant(95) => grant_signal(95),
3027	grant(96) => grant_signal(96),
3028	grant(97) => grant_signal(97),
3029	grant(98) => grant_signal(98),
3030	grant(99) => grant_signal(99),
3031	grant(100) => grant_signal(100),
3032	grant(101) => grant_signal(101),
3033	grant(102) => grant_signal(102),
3034	grant(103) => grant_signal(103),
3035	grant(104) => grant_signal(104),
3036	fifo_full =>fifo_in_full(8),
3037	priority_rotation => priority_rotation_signal(8),
3038	fifo_empty => fifo_in_empty(8),
3039	data_out =>crossbar_in_port8,
3040	data_out_pulse =>crossbar_in_pulse8,
3041	request(92) =>request_signal(92),
3042	request(93) =>request_signal(93),
3043	request(94) =>request_signal(94),
3044	request(95) =>request_signal(95),
3045	request(96) =>request_signal(96),
3046	request(97) =>request_signal(97),
3047	request(98) =>request_signal(98),
3048	request(99) =>request_signal(99),
3049	request(100) =>request_signal(100),
3050	request(101) =>request_signal(101),
3051	request(102) =>request_signal(102),
3052	request(103) =>request_signal(103),
3053	request(104) =>request_signal(104)
3054	);
3055
3056	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3057	GENERIC MAP(number_of_ports =>13)
3058	PORT MAP(
3059	data_in => Port9_in,
3060	data_in_en => data_in_en(9),
3061	reset => reset,
3062	clk =>clk,
3063	grant(105) => grant_signal(105),
3064	grant(106) => grant_signal(106),
3065	grant(107) => grant_signal(107),
3066	grant(108) => grant_signal(108),
3067	grant(109) => grant_signal(109),
3068	grant(110) => grant_signal(110),
3069	grant(111) => grant_signal(111),
3070	grant(112) => grant_signal(112),
3071	grant(113) => grant_signal(113),
3072	grant(114) => grant_signal(114),
3073	grant(115) => grant_signal(115),
3074	grant(116) => grant_signal(116),
3075	grant(117) => grant_signal(117),
3076	fifo_full =>fifo_in_full(9),
3077	priority_rotation => priority_rotation_signal(9),
3078	fifo_empty => fifo_in_empty(9),
3079	data_out =>crossbar_in_port9,
3080	data_out_pulse =>crossbar_in_pulse9,
3081	request(105) =>request_signal(105),
3082	request(106) =>request_signal(106),
3083	request(107) =>request_signal(107),
3084	request(108) =>request_signal(108),
3085	request(109) =>request_signal(109),
3086	request(110) =>request_signal(110),
3087	request(111) =>request_signal(111),
3088	request(112) =>request_signal(112),
3089	request(113) =>request_signal(113),
3090	request(114) =>request_signal(114),
3091	request(115) =>request_signal(115),
3092	request(116) =>request_signal(116),
3093	request(117) =>request_signal(117)
3094	);
3095
3096	PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3097	GENERIC MAP(number_of_ports =>13)
3098	PORT MAP(
3099	data_in => Port10_in,
3100	data_in_en => data_in_en(10),
3101	reset => reset,
3102	clk =>clk,
3103	grant(118) => grant_signal(118),
3104	grant(119) => grant_signal(119),
3105	grant(120) => grant_signal(120),
3106	grant(121) => grant_signal(121),
3107	grant(122) => grant_signal(122),
3108	grant(123) => grant_signal(123),
3109	grant(124) => grant_signal(124),
3110	grant(125) => grant_signal(125),
3111	grant(126) => grant_signal(126),
3112	grant(127) => grant_signal(127),
3113	grant(128) => grant_signal(128),
3114	grant(129) => grant_signal(129),
3115	grant(130) => grant_signal(130),
3116	fifo_full =>fifo_in_full(10),
3117	priority_rotation => priority_rotation_signal(10),
3118	fifo_empty => fifo_in_empty(10),
3119	data_out =>crossbar_in_port10,
3120	data_out_pulse =>crossbar_in_pulse10,
3121	request(118) =>request_signal(118),
3122	request(119) =>request_signal(119),
3123	request(120) =>request_signal(120),
3124	request(121) =>request_signal(121),
3125	request(122) =>request_signal(122),
3126	request(123) =>request_signal(123),
3127	request(124) =>request_signal(124),
3128	request(125) =>request_signal(125),
3129	request(126) =>request_signal(126),
3130	request(127) =>request_signal(127),
3131	request(128) =>request_signal(128),
3132	request(129) =>request_signal(129),
3133	request(130) =>request_signal(130)
3134	);
3135
3136	PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3137	GENERIC MAP(number_of_ports =>13)
3138	PORT MAP(
3139	data_in => Port11_in,
3140	data_in_en => data_in_en(11),
3141	reset => reset,
3142	clk =>clk,
3143	grant(131) => grant_signal(131),
3144	grant(132) => grant_signal(132),
3145	grant(133) => grant_signal(133),
3146	grant(134) => grant_signal(134),
3147	grant(135) => grant_signal(135),
3148	grant(136) => grant_signal(136),
3149	grant(137) => grant_signal(137),
3150	grant(138) => grant_signal(138),
3151	grant(139) => grant_signal(139),
3152	grant(140) => grant_signal(140),
3153	grant(141) => grant_signal(141),
3154	grant(142) => grant_signal(142),
3155	grant(143) => grant_signal(143),
3156	fifo_full =>fifo_in_full(11),
3157	priority_rotation => priority_rotation_signal(11),
3158	fifo_empty => fifo_in_empty(11),
3159	data_out =>crossbar_in_port11,
3160	data_out_pulse =>crossbar_in_pulse11,
3161	request(131) =>request_signal(131),
3162	request(132) =>request_signal(132),
3163	request(133) =>request_signal(133),
3164	request(134) =>request_signal(134),
3165	request(135) =>request_signal(135),
3166	request(136) =>request_signal(136),
3167	request(137) =>request_signal(137),
3168	request(138) =>request_signal(138),
3169	request(139) =>request_signal(139),
3170	request(140) =>request_signal(140),
3171	request(141) =>request_signal(141),
3172	request(142) =>request_signal(142),
3173	request(143) =>request_signal(143)
3174	);
3175
3176	PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3177	GENERIC MAP(number_of_ports =>13)
3178	PORT MAP(
3179	data_in => Port12_in,
3180	data_in_en => data_in_en(12),
3181	reset => reset,
3182	clk =>clk,
3183	grant(144) => grant_signal(144),
3184	grant(145) => grant_signal(145),
3185	grant(146) => grant_signal(146),
3186	grant(147) => grant_signal(147),
3187	grant(148) => grant_signal(148),
3188	grant(149) => grant_signal(149),
3189	grant(150) => grant_signal(150),
3190	grant(151) => grant_signal(151),
3191	grant(152) => grant_signal(152),
3192	grant(153) => grant_signal(153),
3193	grant(154) => grant_signal(154),
3194	grant(155) => grant_signal(155),
3195	grant(156) => grant_signal(156),
3196	fifo_full =>fifo_in_full(12),
3197	priority_rotation => priority_rotation_signal(12),
3198	fifo_empty => fifo_in_empty(12),
3199	data_out =>crossbar_in_port12,
3200	data_out_pulse =>crossbar_in_pulse12,
3201	request(144) =>request_signal(144),
3202	request(145) =>request_signal(145),
3203	request(146) =>request_signal(146),
3204	request(147) =>request_signal(147),
3205	request(148) =>request_signal(148),
3206	request(149) =>request_signal(149),
3207	request(150) =>request_signal(150),
3208	request(151) =>request_signal(151),
3209	request(152) =>request_signal(152),
3210	request(153) =>request_signal(153),
3211	request(154) =>request_signal(154),
3212	request(155) =>request_signal(155),
3213	request(156) =>request_signal(156)
3214	);
3215
3216	PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3217	GENERIC MAP(number_of_ports =>13)
3218	PORT MAP(
3219	data_in => Port13_in,
3220	data_in_en => data_in_en(13),
3221	reset => reset,
3222	clk =>clk,
3223	grant(157) => grant_signal(157),
3224	grant(158) => grant_signal(158),
3225	grant(159) => grant_signal(159),
3226	grant(160) => grant_signal(160),
3227	grant(161) => grant_signal(161),
3228	grant(162) => grant_signal(162),
3229	grant(163) => grant_signal(163),
3230	grant(164) => grant_signal(164),
3231	grant(165) => grant_signal(165),
3232	grant(166) => grant_signal(166),
3233	grant(167) => grant_signal(167),
3234	grant(168) => grant_signal(168),
3235	grant(169) => grant_signal(169),
3236	fifo_full =>fifo_in_full(13),
3237	priority_rotation => priority_rotation_signal(13),
3238	fifo_empty => fifo_in_empty(13),
3239	data_out =>crossbar_in_port13,
3240	data_out_pulse =>crossbar_in_pulse13,
3241	request(157) =>request_signal(157),
3242	request(158) =>request_signal(158),
3243	request(159) =>request_signal(159),
3244	request(160) =>request_signal(160),
3245	request(161) =>request_signal(161),
3246	request(162) =>request_signal(162),
3247	request(163) =>request_signal(163),
3248	request(164) =>request_signal(164),
3249	request(165) =>request_signal(165),
3250	request(166) =>request_signal(166),
3251	request(167) =>request_signal(167),
3252	request(168) =>request_signal(168),
3253	request(169) =>request_signal(169)
3254	);
3255
3256	end generate switch13x13;
3257
3258
3259	-- switch 14 ports
3260	switch14x14 : if number_of_ports = 14 generate
3261
3262	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3263	GENERIC MAP(number_of_ports =>14)
3264	PORT MAP(
3265	data_in => Port1_in,
3266	data_in_en => data_in_en(1),
3267	reset => reset,
3268	clk =>clk,
3269	grant(1) => grant_signal(1),
3270	grant(2) => grant_signal(2),
3271	grant(3) => grant_signal(3),
3272	grant(4) => grant_signal(4),
3273	grant(5) => grant_signal(5),
3274	grant(6) => grant_signal(6),
3275	grant(7) => grant_signal(7),
3276	grant(8) => grant_signal(8),
3277	grant(9) => grant_signal(9),
3278	grant(10) => grant_signal(10),
3279	grant(11) => grant_signal(11),
3280	grant(12) => grant_signal(12),
3281	grant(13) => grant_signal(13),
3282	grant(14) => grant_signal(14),
3283	fifo_full =>fifo_in_full(1),
3284	priority_rotation => priority_rotation_signal(1),
3285	fifo_empty => fifo_in_empty(1),
3286	data_out =>crossbar_in_port1,
3287	data_out_pulse =>crossbar_in_pulse1,
3288	request(1) =>request_signal(1),
3289	request(2) =>request_signal(2),
3290	request(3) =>request_signal(3),
3291	request(4) =>request_signal(4),
3292	request(5) =>request_signal(5),
3293	request(6) =>request_signal(6),
3294	request(7) =>request_signal(7),
3295	request(8) =>request_signal(8),
3296	request(9) =>request_signal(9),
3297	request(10) =>request_signal(10),
3298	request(11) =>request_signal(11),
3299	request(12) =>request_signal(12),
3300	request(13) =>request_signal(13),
3301	request(14) =>request_signal(14)
3302	);
3303
3304	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3305	GENERIC MAP(number_of_ports =>14)
3306	PORT MAP(
3307	data_in => Port2_in,
3308	data_in_en => data_in_en(2),
3309	reset => reset,
3310	clk =>clk,
3311	grant(15) => grant_signal(15),
3312	grant(16) => grant_signal(16),
3313	grant(17) => grant_signal(17),
3314	grant(18) => grant_signal(18),
3315	grant(19) => grant_signal(19),
3316	grant(20) => grant_signal(20),
3317	grant(21) => grant_signal(21),
3318	grant(22) => grant_signal(22),
3319	grant(23) => grant_signal(23),
3320	grant(24) => grant_signal(24),
3321	grant(25) => grant_signal(25),
3322	grant(26) => grant_signal(26),
3323	grant(27) => grant_signal(27),
3324	grant(28) => grant_signal(28),
3325	fifo_full =>fifo_in_full(2),
3326	priority_rotation => priority_rotation_signal(2),
3327	fifo_empty => fifo_in_empty(2),
3328	data_out =>crossbar_in_port2,
3329	data_out_pulse =>crossbar_in_pulse2,
3330	request(15) =>request_signal(15),
3331	request(16) =>request_signal(16),
3332	request(17) =>request_signal(17),
3333	request(18) =>request_signal(18),
3334	request(19) =>request_signal(19),
3335	request(20) =>request_signal(20),
3336	request(21) =>request_signal(21),
3337	request(22) =>request_signal(22),
3338	request(23) =>request_signal(23),
3339	request(24) =>request_signal(24),
3340	request(25) =>request_signal(25),
3341	request(26) =>request_signal(26),
3342	request(27) =>request_signal(27),
3343	request(28) =>request_signal(28)
3344	);
3345
3346	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3347	GENERIC MAP(number_of_ports =>14)
3348	PORT MAP(
3349	data_in => Port3_in,
3350	data_in_en => data_in_en(3),
3351	reset => reset,
3352	clk =>clk,
3353	grant(29) => grant_signal(29),
3354	grant(30) => grant_signal(30),
3355	grant(31) => grant_signal(31),
3356	grant(32) => grant_signal(32),
3357	grant(33) => grant_signal(33),
3358	grant(34) => grant_signal(34),
3359	grant(35) => grant_signal(35),
3360	grant(36) => grant_signal(36),
3361	grant(37) => grant_signal(37),
3362	grant(38) => grant_signal(38),
3363	grant(39) => grant_signal(39),
3364	grant(40) => grant_signal(40),
3365	grant(41) => grant_signal(41),
3366	grant(42) => grant_signal(42),
3367	fifo_full =>fifo_in_full(3),
3368	priority_rotation => priority_rotation_signal(3),
3369	fifo_empty => fifo_in_empty(3),
3370	data_out =>crossbar_in_port3,
3371	data_out_pulse =>crossbar_in_pulse3,
3372	request(29) =>request_signal(29),
3373	request(30) =>request_signal(30),
3374	request(31) =>request_signal(31),
3375	request(32) =>request_signal(32),
3376	request(33) =>request_signal(33),
3377	request(34) =>request_signal(34),
3378	request(35) =>request_signal(35),
3379	request(36) =>request_signal(36),
3380	request(37) =>request_signal(37),
3381	request(38) =>request_signal(38),
3382	request(39) =>request_signal(39),
3383	request(40) =>request_signal(40),
3384	request(41) =>request_signal(41),
3385	request(42) =>request_signal(42)
3386	);
3387
3388	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3389	GENERIC MAP(number_of_ports =>14)
3390	PORT MAP(
3391	data_in => Port4_in,
3392	data_in_en => data_in_en(4),
3393	reset => reset,
3394	clk =>clk,
3395	grant(43) => grant_signal(43),
3396	grant(44) => grant_signal(44),
3397	grant(45) => grant_signal(45),
3398	grant(46) => grant_signal(46),
3399	grant(47) => grant_signal(47),
3400	grant(48) => grant_signal(48),
3401	grant(49) => grant_signal(49),
3402	grant(50) => grant_signal(50),
3403	grant(51) => grant_signal(51),
3404	grant(52) => grant_signal(52),
3405	grant(53) => grant_signal(53),
3406	grant(54) => grant_signal(54),
3407	grant(55) => grant_signal(55),
3408	grant(56) => grant_signal(56),
3409	fifo_full =>fifo_in_full(4),
3410	priority_rotation => priority_rotation_signal(4),
3411	fifo_empty => fifo_in_empty(4),
3412	data_out =>crossbar_in_port4,
3413	data_out_pulse =>crossbar_in_pulse4,
3414	request(43) =>request_signal(43),
3415	request(44) =>request_signal(44),
3416	request(45) =>request_signal(45),
3417	request(46) =>request_signal(46),
3418	request(47) =>request_signal(47),
3419	request(48) =>request_signal(48),
3420	request(49) =>request_signal(49),
3421	request(50) =>request_signal(50),
3422	request(51) =>request_signal(51),
3423	request(52) =>request_signal(52),
3424	request(53) =>request_signal(53),
3425	request(54) =>request_signal(54),
3426	request(55) =>request_signal(55),
3427	request(56) =>request_signal(56)
3428	);
3429
3430	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3431	GENERIC MAP(number_of_ports =>14)
3432	PORT MAP(
3433	data_in => Port5_in,
3434	data_in_en => data_in_en(5),
3435	reset => reset,
3436	clk =>clk,
3437	grant(57) => grant_signal(57),
3438	grant(58) => grant_signal(58),
3439	grant(59) => grant_signal(59),
3440	grant(60) => grant_signal(60),
3441	grant(61) => grant_signal(61),
3442	grant(62) => grant_signal(62),
3443	grant(63) => grant_signal(63),
3444	grant(64) => grant_signal(64),
3445	grant(65) => grant_signal(65),
3446	grant(66) => grant_signal(66),
3447	grant(67) => grant_signal(67),
3448	grant(68) => grant_signal(68),
3449	grant(69) => grant_signal(69),
3450	grant(70) => grant_signal(70),
3451	fifo_full =>fifo_in_full(5),
3452	priority_rotation => priority_rotation_signal(5),
3453	fifo_empty => fifo_in_empty(5),
3454	data_out =>crossbar_in_port5,
3455	data_out_pulse =>crossbar_in_pulse5,
3456	request(57) =>request_signal(57),
3457	request(58) =>request_signal(58),
3458	request(59) =>request_signal(59),
3459	request(60) =>request_signal(60),
3460	request(61) =>request_signal(61),
3461	request(62) =>request_signal(62),
3462	request(63) =>request_signal(63),
3463	request(64) =>request_signal(64),
3464	request(65) =>request_signal(65),
3465	request(66) =>request_signal(66),
3466	request(67) =>request_signal(67),
3467	request(68) =>request_signal(68),
3468	request(69) =>request_signal(69),
3469	request(70) =>request_signal(70)
3470	);
3471
3472	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3473	GENERIC MAP(number_of_ports =>14)
3474	PORT MAP(
3475	data_in => Port6_in,
3476	data_in_en => data_in_en(6),
3477	reset => reset,
3478	clk =>clk,
3479	grant(71) => grant_signal(71),
3480	grant(72) => grant_signal(72),
3481	grant(73) => grant_signal(73),
3482	grant(74) => grant_signal(74),
3483	grant(75) => grant_signal(75),
3484	grant(76) => grant_signal(76),
3485	grant(77) => grant_signal(77),
3486	grant(78) => grant_signal(78),
3487	grant(79) => grant_signal(79),
3488	grant(80) => grant_signal(80),
3489	grant(81) => grant_signal(81),
3490	grant(82) => grant_signal(82),
3491	grant(83) => grant_signal(83),
3492	grant(84) => grant_signal(84),
3493	fifo_full =>fifo_in_full(6),
3494	priority_rotation => priority_rotation_signal(6),
3495	fifo_empty => fifo_in_empty(6),
3496	data_out =>crossbar_in_port6,
3497	data_out_pulse =>crossbar_in_pulse6,
3498	request(71) =>request_signal(71),
3499	request(72) =>request_signal(72),
3500	request(73) =>request_signal(73),
3501	request(74) =>request_signal(74),
3502	request(75) =>request_signal(75),
3503	request(76) =>request_signal(76),
3504	request(77) =>request_signal(77),
3505	request(78) =>request_signal(78),
3506	request(79) =>request_signal(79),
3507	request(80) =>request_signal(80),
3508	request(81) =>request_signal(81),
3509	request(82) =>request_signal(82),
3510	request(83) =>request_signal(83),
3511	request(84) =>request_signal(84)
3512	);
3513
3514	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3515	GENERIC MAP(number_of_ports =>14)
3516	PORT MAP(
3517	data_in => Port7_in,
3518	data_in_en => data_in_en(7),
3519	reset => reset,
3520	clk =>clk,
3521	grant(85) => grant_signal(85),
3522	grant(86) => grant_signal(86),
3523	grant(87) => grant_signal(87),
3524	grant(88) => grant_signal(88),
3525	grant(89) => grant_signal(89),
3526	grant(90) => grant_signal(90),
3527	grant(91) => grant_signal(91),
3528	grant(92) => grant_signal(92),
3529	grant(93) => grant_signal(93),
3530	grant(94) => grant_signal(94),
3531	grant(95) => grant_signal(95),
3532	grant(96) => grant_signal(96),
3533	grant(97) => grant_signal(97),
3534	grant(98) => grant_signal(98),
3535	fifo_full =>fifo_in_full(7),
3536	priority_rotation => priority_rotation_signal(7),
3537	fifo_empty => fifo_in_empty(7),
3538	data_out =>crossbar_in_port7,
3539	data_out_pulse =>crossbar_in_pulse7,
3540	request(85) =>request_signal(85),
3541	request(86) =>request_signal(86),
3542	request(87) =>request_signal(87),
3543	request(88) =>request_signal(88),
3544	request(89) =>request_signal(89),
3545	request(90) =>request_signal(90),
3546	request(91) =>request_signal(91),
3547	request(92) =>request_signal(92),
3548	request(93) =>request_signal(93),
3549	request(94) =>request_signal(94),
3550	request(95) =>request_signal(95),
3551	request(96) =>request_signal(96),
3552	request(97) =>request_signal(97),
3553	request(98) =>request_signal(98)
3554	);
3555
3556	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3557	GENERIC MAP(number_of_ports =>14)
3558	PORT MAP(
3559	data_in => Port8_in,
3560	data_in_en => data_in_en(8),
3561	reset => reset,
3562	clk =>clk,
3563	grant(99) => grant_signal(99),
3564	grant(100) => grant_signal(100),
3565	grant(101) => grant_signal(101),
3566	grant(102) => grant_signal(102),
3567	grant(103) => grant_signal(103),
3568	grant(104) => grant_signal(104),
3569	grant(105) => grant_signal(105),
3570	grant(106) => grant_signal(106),
3571	grant(107) => grant_signal(107),
3572	grant(108) => grant_signal(108),
3573	grant(109) => grant_signal(109),
3574	grant(110) => grant_signal(110),
3575	grant(111) => grant_signal(111),
3576	grant(112) => grant_signal(112),
3577	fifo_full =>fifo_in_full(8),
3578	priority_rotation => priority_rotation_signal(8),
3579	fifo_empty => fifo_in_empty(8),
3580	data_out =>crossbar_in_port8,
3581	data_out_pulse =>crossbar_in_pulse8,
3582	request(99) =>request_signal(99),
3583	request(100) =>request_signal(100),
3584	request(101) =>request_signal(101),
3585	request(102) =>request_signal(102),
3586	request(103) =>request_signal(103),
3587	request(104) =>request_signal(104),
3588	request(105) =>request_signal(105),
3589	request(106) =>request_signal(106),
3590	request(107) =>request_signal(107),
3591	request(108) =>request_signal(108),
3592	request(109) =>request_signal(109),
3593	request(110) =>request_signal(110),
3594	request(111) =>request_signal(111),
3595	request(112) =>request_signal(112)
3596	);
3597
3598	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3599	GENERIC MAP(number_of_ports =>14)
3600	PORT MAP(
3601	data_in => Port9_in,
3602	data_in_en => data_in_en(9),
3603	reset => reset,
3604	clk =>clk,
3605	grant(113) => grant_signal(113),
3606	grant(114) => grant_signal(114),
3607	grant(115) => grant_signal(115),
3608	grant(116) => grant_signal(116),
3609	grant(117) => grant_signal(117),
3610	grant(118) => grant_signal(118),
3611	grant(119) => grant_signal(119),
3612	grant(120) => grant_signal(120),
3613	grant(121) => grant_signal(121),
3614	grant(122) => grant_signal(122),
3615	grant(123) => grant_signal(123),
3616	grant(124) => grant_signal(124),
3617	grant(125) => grant_signal(125),
3618	grant(126) => grant_signal(126),
3619	fifo_full =>fifo_in_full(9),
3620	priority_rotation => priority_rotation_signal(9),
3621	fifo_empty => fifo_in_empty(9),
3622	data_out =>crossbar_in_port9,
3623	data_out_pulse =>crossbar_in_pulse9,
3624	request(113) =>request_signal(113),
3625	request(114) =>request_signal(114),
3626	request(115) =>request_signal(115),
3627	request(116) =>request_signal(116),
3628	request(117) =>request_signal(117),
3629	request(118) =>request_signal(118),
3630	request(119) =>request_signal(119),
3631	request(120) =>request_signal(120),
3632	request(121) =>request_signal(121),
3633	request(122) =>request_signal(122),
3634	request(123) =>request_signal(123),
3635	request(124) =>request_signal(124),
3636	request(125) =>request_signal(125),
3637	request(126) =>request_signal(126)
3638	);
3639
3640	PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3641	GENERIC MAP(number_of_ports =>14)
3642	PORT MAP(
3643	data_in => Port10_in,
3644	data_in_en => data_in_en(10),
3645	reset => reset,
3646	clk =>clk,
3647	grant(127) => grant_signal(127),
3648	grant(128) => grant_signal(128),
3649	grant(129) => grant_signal(129),
3650	grant(130) => grant_signal(130),
3651	grant(131) => grant_signal(131),
3652	grant(132) => grant_signal(132),
3653	grant(133) => grant_signal(133),
3654	grant(134) => grant_signal(134),
3655	grant(135) => grant_signal(135),
3656	grant(136) => grant_signal(136),
3657	grant(137) => grant_signal(137),
3658	grant(138) => grant_signal(138),
3659	grant(139) => grant_signal(139),
3660	grant(140) => grant_signal(140),
3661	fifo_full =>fifo_in_full(10),
3662	priority_rotation => priority_rotation_signal(10),
3663	fifo_empty => fifo_in_empty(10),
3664	data_out =>crossbar_in_port10,
3665	data_out_pulse =>crossbar_in_pulse10,
3666	request(127) =>request_signal(127),
3667	request(128) =>request_signal(128),
3668	request(129) =>request_signal(129),
3669	request(130) =>request_signal(130),
3670	request(131) =>request_signal(131),
3671	request(132) =>request_signal(132),
3672	request(133) =>request_signal(133),
3673	request(134) =>request_signal(134),
3674	request(135) =>request_signal(135),
3675	request(136) =>request_signal(136),
3676	request(137) =>request_signal(137),
3677	request(138) =>request_signal(138),
3678	request(139) =>request_signal(139),
3679	request(140) =>request_signal(140)
3680	);
3681
3682	PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3683	GENERIC MAP(number_of_ports =>14)
3684	PORT MAP(
3685	data_in => Port11_in,
3686	data_in_en => data_in_en(11),
3687	reset => reset,
3688	clk =>clk,
3689	grant(141) => grant_signal(141),
3690	grant(142) => grant_signal(142),
3691	grant(143) => grant_signal(143),
3692	grant(144) => grant_signal(144),
3693	grant(145) => grant_signal(145),
3694	grant(146) => grant_signal(146),
3695	grant(147) => grant_signal(147),
3696	grant(148) => grant_signal(148),
3697	grant(149) => grant_signal(149),
3698	grant(150) => grant_signal(150),
3699	grant(151) => grant_signal(151),
3700	grant(152) => grant_signal(152),
3701	grant(153) => grant_signal(153),
3702	grant(154) => grant_signal(154),
3703	fifo_full =>fifo_in_full(11),
3704	priority_rotation => priority_rotation_signal(11),
3705	fifo_empty => fifo_in_empty(11),
3706	data_out =>crossbar_in_port11,
3707	data_out_pulse =>crossbar_in_pulse11,
3708	request(141) =>request_signal(141),
3709	request(142) =>request_signal(142),
3710	request(143) =>request_signal(143),
3711	request(144) =>request_signal(144),
3712	request(145) =>request_signal(145),
3713	request(146) =>request_signal(146),
3714	request(147) =>request_signal(147),
3715	request(148) =>request_signal(148),
3716	request(149) =>request_signal(149),
3717	request(150) =>request_signal(150),
3718	request(151) =>request_signal(151),
3719	request(152) =>request_signal(152),
3720	request(153) =>request_signal(153),
3721	request(154) =>request_signal(154)
3722	);
3723
3724	PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3725	GENERIC MAP(number_of_ports =>14)
3726	PORT MAP(
3727	data_in => Port12_in,
3728	data_in_en => data_in_en(12),
3729	reset => reset,
3730	clk =>clk,
3731	grant(155) => grant_signal(155),
3732	grant(156) => grant_signal(156),
3733	grant(157) => grant_signal(157),
3734	grant(158) => grant_signal(158),
3735	grant(159) => grant_signal(159),
3736	grant(160) => grant_signal(160),
3737	grant(161) => grant_signal(161),
3738	grant(162) => grant_signal(162),
3739	grant(163) => grant_signal(163),
3740	grant(164) => grant_signal(164),
3741	grant(165) => grant_signal(165),
3742	grant(166) => grant_signal(166),
3743	grant(167) => grant_signal(167),
3744	grant(168) => grant_signal(168),
3745	fifo_full =>fifo_in_full(12),
3746	priority_rotation => priority_rotation_signal(12),
3747	fifo_empty => fifo_in_empty(12),
3748	data_out =>crossbar_in_port12,
3749	data_out_pulse =>crossbar_in_pulse12,
3750	request(155) =>request_signal(155),
3751	request(156) =>request_signal(156),
3752	request(157) =>request_signal(157),
3753	request(158) =>request_signal(158),
3754	request(159) =>request_signal(159),
3755	request(160) =>request_signal(160),
3756	request(161) =>request_signal(161),
3757	request(162) =>request_signal(162),
3758	request(163) =>request_signal(163),
3759	request(164) =>request_signal(164),
3760	request(165) =>request_signal(165),
3761	request(166) =>request_signal(166),
3762	request(167) =>request_signal(167),
3763	request(168) =>request_signal(168)
3764	);
3765
3766	PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3767	GENERIC MAP(number_of_ports =>14)
3768	PORT MAP(
3769	data_in => Port13_in,
3770	data_in_en => data_in_en(13),
3771	reset => reset,
3772	clk =>clk,
3773	grant(169) => grant_signal(169),
3774	grant(170) => grant_signal(170),
3775	grant(171) => grant_signal(171),
3776	grant(172) => grant_signal(172),
3777	grant(173) => grant_signal(173),
3778	grant(174) => grant_signal(174),
3779	grant(175) => grant_signal(175),
3780	grant(176) => grant_signal(176),
3781	grant(177) => grant_signal(177),
3782	grant(178) => grant_signal(178),
3783	grant(179) => grant_signal(179),
3784	grant(180) => grant_signal(180),
3785	grant(181) => grant_signal(181),
3786	grant(182) => grant_signal(182),
3787	fifo_full =>fifo_in_full(13),
3788	priority_rotation => priority_rotation_signal(13),
3789	fifo_empty => fifo_in_empty(13),
3790	data_out =>crossbar_in_port13,
3791	data_out_pulse =>crossbar_in_pulse13,
3792	request(169) =>request_signal(169),
3793	request(170) =>request_signal(170),
3794	request(171) =>request_signal(171),
3795	request(172) =>request_signal(172),
3796	request(173) =>request_signal(173),
3797	request(174) =>request_signal(174),
3798	request(175) =>request_signal(175),
3799	request(176) =>request_signal(176),
3800	request(177) =>request_signal(177),
3801	request(178) =>request_signal(178),
3802	request(179) =>request_signal(179),
3803	request(180) =>request_signal(180),
3804	request(181) =>request_signal(181),
3805	request(182) =>request_signal(182)
3806	);
3807
3808	PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3809	GENERIC MAP(number_of_ports =>14)
3810	PORT MAP(
3811	data_in => Port14_in,
3812	data_in_en => data_in_en(14),
3813	reset => reset,
3814	clk =>clk,
3815	grant(183) => grant_signal(183),
3816	grant(184) => grant_signal(184),
3817	grant(185) => grant_signal(185),
3818	grant(186) => grant_signal(186),
3819	grant(187) => grant_signal(187),
3820	grant(188) => grant_signal(188),
3821	grant(189) => grant_signal(189),
3822	grant(190) => grant_signal(190),
3823	grant(191) => grant_signal(191),
3824	grant(192) => grant_signal(192),
3825	grant(193) => grant_signal(193),
3826	grant(194) => grant_signal(194),
3827	grant(195) => grant_signal(195),
3828	grant(196) => grant_signal(196),
3829	fifo_full =>fifo_in_full(14),
3830	priority_rotation => priority_rotation_signal(14),
3831	fifo_empty => fifo_in_empty(14),
3832	data_out =>crossbar_in_port14,
3833	data_out_pulse =>crossbar_in_pulse14,
3834	request(183) =>request_signal(183),
3835	request(184) =>request_signal(184),
3836	request(185) =>request_signal(185),
3837	request(186) =>request_signal(186),
3838	request(187) =>request_signal(187),
3839	request(188) =>request_signal(188),
3840	request(189) =>request_signal(189),
3841	request(190) =>request_signal(190),
3842	request(191) =>request_signal(191),
3843	request(192) =>request_signal(192),
3844	request(193) =>request_signal(193),
3845	request(194) =>request_signal(194),
3846	request(195) =>request_signal(195),
3847	request(196) =>request_signal(196)
3848	);
3849
3850	end generate switch14x14;
3851
3852
3853	-- switch 15 ports
3854	switch15x15 : if number_of_ports = 15 generate
3855
3856	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3857	GENERIC MAP(number_of_ports =>15)
3858	PORT MAP(
3859	data_in => Port1_in,
3860	data_in_en => data_in_en(1),
3861	reset => reset,
3862	clk =>clk,
3863	grant(1) => grant_signal(1),
3864	grant(2) => grant_signal(2),
3865	grant(3) => grant_signal(3),
3866	grant(4) => grant_signal(4),
3867	grant(5) => grant_signal(5),
3868	grant(6) => grant_signal(6),
3869	grant(7) => grant_signal(7),
3870	grant(8) => grant_signal(8),
3871	grant(9) => grant_signal(9),
3872	grant(10) => grant_signal(10),
3873	grant(11) => grant_signal(11),
3874	grant(12) => grant_signal(12),
3875	grant(13) => grant_signal(13),
3876	grant(14) => grant_signal(14),
3877	grant(15) => grant_signal(15),
3878	fifo_full =>fifo_in_full(1),
3879	priority_rotation => priority_rotation_signal(1),
3880	fifo_empty => fifo_in_empty(1),
3881	data_out =>crossbar_in_port1,
3882	data_out_pulse =>crossbar_in_pulse1,
3883	request(1) =>request_signal(1),
3884	request(2) =>request_signal(2),
3885	request(3) =>request_signal(3),
3886	request(4) =>request_signal(4),
3887	request(5) =>request_signal(5),
3888	request(6) =>request_signal(6),
3889	request(7) =>request_signal(7),
3890	request(8) =>request_signal(8),
3891	request(9) =>request_signal(9),
3892	request(10) =>request_signal(10),
3893	request(11) =>request_signal(11),
3894	request(12) =>request_signal(12),
3895	request(13) =>request_signal(13),
3896	request(14) =>request_signal(14),
3897	request(15) =>request_signal(15)
3898	);
3899
3900	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3901	GENERIC MAP(number_of_ports =>15)
3902	PORT MAP(
3903	data_in => Port2_in,
3904	data_in_en => data_in_en(2),
3905	reset => reset,
3906	clk =>clk,
3907	grant(16) => grant_signal(16),
3908	grant(17) => grant_signal(17),
3909	grant(18) => grant_signal(18),
3910	grant(19) => grant_signal(19),
3911	grant(20) => grant_signal(20),
3912	grant(21) => grant_signal(21),
3913	grant(22) => grant_signal(22),
3914	grant(23) => grant_signal(23),
3915	grant(24) => grant_signal(24),
3916	grant(25) => grant_signal(25),
3917	grant(26) => grant_signal(26),
3918	grant(27) => grant_signal(27),
3919	grant(28) => grant_signal(28),
3920	grant(29) => grant_signal(29),
3921	grant(30) => grant_signal(30),
3922	fifo_full =>fifo_in_full(2),
3923	priority_rotation => priority_rotation_signal(2),
3924	fifo_empty => fifo_in_empty(2),
3925	data_out =>crossbar_in_port2,
3926	data_out_pulse =>crossbar_in_pulse2,
3927	request(16) =>request_signal(16),
3928	request(17) =>request_signal(17),
3929	request(18) =>request_signal(18),
3930	request(19) =>request_signal(19),
3931	request(20) =>request_signal(20),
3932	request(21) =>request_signal(21),
3933	request(22) =>request_signal(22),
3934	request(23) =>request_signal(23),
3935	request(24) =>request_signal(24),
3936	request(25) =>request_signal(25),
3937	request(26) =>request_signal(26),
3938	request(27) =>request_signal(27),
3939	request(28) =>request_signal(28),
3940	request(29) =>request_signal(29),
3941	request(30) =>request_signal(30)
3942	);
3943
3944	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3945	GENERIC MAP(number_of_ports =>15)
3946	PORT MAP(
3947	data_in => Port3_in,
3948	data_in_en => data_in_en(3),
3949	reset => reset,
3950	clk =>clk,
3951	grant(31) => grant_signal(31),
3952	grant(32) => grant_signal(32),
3953	grant(33) => grant_signal(33),
3954	grant(34) => grant_signal(34),
3955	grant(35) => grant_signal(35),
3956	grant(36) => grant_signal(36),
3957	grant(37) => grant_signal(37),
3958	grant(38) => grant_signal(38),
3959	grant(39) => grant_signal(39),
3960	grant(40) => grant_signal(40),
3961	grant(41) => grant_signal(41),
3962	grant(42) => grant_signal(42),
3963	grant(43) => grant_signal(43),
3964	grant(44) => grant_signal(44),
3965	grant(45) => grant_signal(45),
3966	fifo_full =>fifo_in_full(3),
3967	priority_rotation => priority_rotation_signal(3),
3968	fifo_empty => fifo_in_empty(3),
3969	data_out =>crossbar_in_port3,
3970	data_out_pulse =>crossbar_in_pulse3,
3971	request(31) =>request_signal(31),
3972	request(32) =>request_signal(32),
3973	request(33) =>request_signal(33),
3974	request(34) =>request_signal(34),
3975	request(35) =>request_signal(35),
3976	request(36) =>request_signal(36),
3977	request(37) =>request_signal(37),
3978	request(38) =>request_signal(38),
3979	request(39) =>request_signal(39),
3980	request(40) =>request_signal(40),
3981	request(41) =>request_signal(41),
3982	request(42) =>request_signal(42),
3983	request(43) =>request_signal(43),
3984	request(44) =>request_signal(44),
3985	request(45) =>request_signal(45)
3986	);
3987
3988	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
3989	GENERIC MAP(number_of_ports =>15)
3990	PORT MAP(
3991	data_in => Port4_in,
3992	data_in_en => data_in_en(4),
3993	reset => reset,
3994	clk =>clk,
3995	grant(46) => grant_signal(46),
3996	grant(47) => grant_signal(47),
3997	grant(48) => grant_signal(48),
3998	grant(49) => grant_signal(49),
3999	grant(50) => grant_signal(50),
4000	grant(51) => grant_signal(51),
4001	grant(52) => grant_signal(52),
4002	grant(53) => grant_signal(53),
4003	grant(54) => grant_signal(54),
4004	grant(55) => grant_signal(55),
4005	grant(56) => grant_signal(56),
4006	grant(57) => grant_signal(57),
4007	grant(58) => grant_signal(58),
4008	grant(59) => grant_signal(59),
4009	grant(60) => grant_signal(60),
4010	fifo_full =>fifo_in_full(4),
4011	priority_rotation => priority_rotation_signal(4),
4012	fifo_empty => fifo_in_empty(4),
4013	data_out =>crossbar_in_port4,
4014	data_out_pulse =>crossbar_in_pulse4,
4015	request(46) =>request_signal(46),
4016	request(47) =>request_signal(47),
4017	request(48) =>request_signal(48),
4018	request(49) =>request_signal(49),
4019	request(50) =>request_signal(50),
4020	request(51) =>request_signal(51),
4021	request(52) =>request_signal(52),
4022	request(53) =>request_signal(53),
4023	request(54) =>request_signal(54),
4024	request(55) =>request_signal(55),
4025	request(56) =>request_signal(56),
4026	request(57) =>request_signal(57),
4027	request(58) =>request_signal(58),
4028	request(59) =>request_signal(59),
4029	request(60) =>request_signal(60)
4030	);
4031
4032	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4033	GENERIC MAP(number_of_ports =>15)
4034	PORT MAP(
4035	data_in => Port5_in,
4036	data_in_en => data_in_en(5),
4037	reset => reset,
4038	clk =>clk,
4039	grant(61) => grant_signal(61),
4040	grant(62) => grant_signal(62),
4041	grant(63) => grant_signal(63),
4042	grant(64) => grant_signal(64),
4043	grant(65) => grant_signal(65),
4044	grant(66) => grant_signal(66),
4045	grant(67) => grant_signal(67),
4046	grant(68) => grant_signal(68),
4047	grant(69) => grant_signal(69),
4048	grant(70) => grant_signal(70),
4049	grant(71) => grant_signal(71),
4050	grant(72) => grant_signal(72),
4051	grant(73) => grant_signal(73),
4052	grant(74) => grant_signal(74),
4053	grant(75) => grant_signal(75),
4054	fifo_full =>fifo_in_full(5),
4055	priority_rotation => priority_rotation_signal(5),
4056	fifo_empty => fifo_in_empty(5),
4057	data_out =>crossbar_in_port5,
4058	data_out_pulse =>crossbar_in_pulse5,
4059	request(61) =>request_signal(61),
4060	request(62) =>request_signal(62),
4061	request(63) =>request_signal(63),
4062	request(64) =>request_signal(64),
4063	request(65) =>request_signal(65),
4064	request(66) =>request_signal(66),
4065	request(67) =>request_signal(67),
4066	request(68) =>request_signal(68),
4067	request(69) =>request_signal(69),
4068	request(70) =>request_signal(70),
4069	request(71) =>request_signal(71),
4070	request(72) =>request_signal(72),
4071	request(73) =>request_signal(73),
4072	request(74) =>request_signal(74),
4073	request(75) =>request_signal(75)
4074	);
4075
4076	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4077	GENERIC MAP(number_of_ports =>15)
4078	PORT MAP(
4079	data_in => Port6_in,
4080	data_in_en => data_in_en(6),
4081	reset => reset,
4082	clk =>clk,
4083	grant(76) => grant_signal(76),
4084	grant(77) => grant_signal(77),
4085	grant(78) => grant_signal(78),
4086	grant(79) => grant_signal(79),
4087	grant(80) => grant_signal(80),
4088	grant(81) => grant_signal(81),
4089	grant(82) => grant_signal(82),
4090	grant(83) => grant_signal(83),
4091	grant(84) => grant_signal(84),
4092	grant(85) => grant_signal(85),
4093	grant(86) => grant_signal(86),
4094	grant(87) => grant_signal(87),
4095	grant(88) => grant_signal(88),
4096	grant(89) => grant_signal(89),
4097	grant(90) => grant_signal(90),
4098	fifo_full =>fifo_in_full(6),
4099	priority_rotation => priority_rotation_signal(6),
4100	fifo_empty => fifo_in_empty(6),
4101	data_out =>crossbar_in_port6,
4102	data_out_pulse =>crossbar_in_pulse6,
4103	request(76) =>request_signal(76),
4104	request(77) =>request_signal(77),
4105	request(78) =>request_signal(78),
4106	request(79) =>request_signal(79),
4107	request(80) =>request_signal(80),
4108	request(81) =>request_signal(81),
4109	request(82) =>request_signal(82),
4110	request(83) =>request_signal(83),
4111	request(84) =>request_signal(84),
4112	request(85) =>request_signal(85),
4113	request(86) =>request_signal(86),
4114	request(87) =>request_signal(87),
4115	request(88) =>request_signal(88),
4116	request(89) =>request_signal(89),
4117	request(90) =>request_signal(90)
4118	);
4119
4120	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4121	GENERIC MAP(number_of_ports =>15)
4122	PORT MAP(
4123	data_in => Port7_in,
4124	data_in_en => data_in_en(7),
4125	reset => reset,
4126	clk =>clk,
4127	grant(91) => grant_signal(91),
4128	grant(92) => grant_signal(92),
4129	grant(93) => grant_signal(93),
4130	grant(94) => grant_signal(94),
4131	grant(95) => grant_signal(95),
4132	grant(96) => grant_signal(96),
4133	grant(97) => grant_signal(97),
4134	grant(98) => grant_signal(98),
4135	grant(99) => grant_signal(99),
4136	grant(100) => grant_signal(100),
4137	grant(101) => grant_signal(101),
4138	grant(102) => grant_signal(102),
4139	grant(103) => grant_signal(103),
4140	grant(104) => grant_signal(104),
4141	grant(105) => grant_signal(105),
4142	fifo_full =>fifo_in_full(7),
4143	priority_rotation => priority_rotation_signal(7),
4144	fifo_empty => fifo_in_empty(7),
4145	data_out =>crossbar_in_port7,
4146	data_out_pulse =>crossbar_in_pulse7,
4147	request(91) =>request_signal(91),
4148	request(92) =>request_signal(92),
4149	request(93) =>request_signal(93),
4150	request(94) =>request_signal(94),
4151	request(95) =>request_signal(95),
4152	request(96) =>request_signal(96),
4153	request(97) =>request_signal(97),
4154	request(98) =>request_signal(98),
4155	request(99) =>request_signal(99),
4156	request(100) =>request_signal(100),
4157	request(101) =>request_signal(101),
4158	request(102) =>request_signal(102),
4159	request(103) =>request_signal(103),
4160	request(104) =>request_signal(104),
4161	request(105) =>request_signal(105)
4162	);
4163
4164	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4165	GENERIC MAP(number_of_ports =>15)
4166	PORT MAP(
4167	data_in => Port8_in,
4168	data_in_en => data_in_en(8),
4169	reset => reset,
4170	clk =>clk,
4171	grant(106) => grant_signal(106),
4172	grant(107) => grant_signal(107),
4173	grant(108) => grant_signal(108),
4174	grant(109) => grant_signal(109),
4175	grant(110) => grant_signal(110),
4176	grant(111) => grant_signal(111),
4177	grant(112) => grant_signal(112),
4178	grant(113) => grant_signal(113),
4179	grant(114) => grant_signal(114),
4180	grant(115) => grant_signal(115),
4181	grant(116) => grant_signal(116),
4182	grant(117) => grant_signal(117),
4183	grant(118) => grant_signal(118),
4184	grant(119) => grant_signal(119),
4185	grant(120) => grant_signal(120),
4186	fifo_full =>fifo_in_full(8),
4187	priority_rotation => priority_rotation_signal(8),
4188	fifo_empty => fifo_in_empty(8),
4189	data_out =>crossbar_in_port8,
4190	data_out_pulse =>crossbar_in_pulse8,
4191	request(106) =>request_signal(106),
4192	request(107) =>request_signal(107),
4193	request(108) =>request_signal(108),
4194	request(109) =>request_signal(109),
4195	request(110) =>request_signal(110),
4196	request(111) =>request_signal(111),
4197	request(112) =>request_signal(112),
4198	request(113) =>request_signal(113),
4199	request(114) =>request_signal(114),
4200	request(115) =>request_signal(115),
4201	request(116) =>request_signal(116),
4202	request(117) =>request_signal(117),
4203	request(118) =>request_signal(118),
4204	request(119) =>request_signal(119),
4205	request(120) =>request_signal(120)
4206	);
4207
4208	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4209	GENERIC MAP(number_of_ports =>15)
4210	PORT MAP(
4211	data_in => Port9_in,
4212	data_in_en => data_in_en(9),
4213	reset => reset,
4214	clk =>clk,
4215	grant(121) => grant_signal(121),
4216	grant(122) => grant_signal(122),
4217	grant(123) => grant_signal(123),
4218	grant(124) => grant_signal(124),
4219	grant(125) => grant_signal(125),
4220	grant(126) => grant_signal(126),
4221	grant(127) => grant_signal(127),
4222	grant(128) => grant_signal(128),
4223	grant(129) => grant_signal(129),
4224	grant(130) => grant_signal(130),
4225	grant(131) => grant_signal(131),
4226	grant(132) => grant_signal(132),
4227	grant(133) => grant_signal(133),
4228	grant(134) => grant_signal(134),
4229	grant(135) => grant_signal(135),
4230	fifo_full =>fifo_in_full(9),
4231	priority_rotation => priority_rotation_signal(9),
4232	fifo_empty => fifo_in_empty(9),
4233	data_out =>crossbar_in_port9,
4234	data_out_pulse =>crossbar_in_pulse9,
4235	request(121) =>request_signal(121),
4236	request(122) =>request_signal(122),
4237	request(123) =>request_signal(123),
4238	request(124) =>request_signal(124),
4239	request(125) =>request_signal(125),
4240	request(126) =>request_signal(126),
4241	request(127) =>request_signal(127),
4242	request(128) =>request_signal(128),
4243	request(129) =>request_signal(129),
4244	request(130) =>request_signal(130),
4245	request(131) =>request_signal(131),
4246	request(132) =>request_signal(132),
4247	request(133) =>request_signal(133),
4248	request(134) =>request_signal(134),
4249	request(135) =>request_signal(135)
4250	);
4251
4252	PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4253	GENERIC MAP(number_of_ports =>15)
4254	PORT MAP(
4255	data_in => Port10_in,
4256	data_in_en => data_in_en(10),
4257	reset => reset,
4258	clk =>clk,
4259	grant(136) => grant_signal(136),
4260	grant(137) => grant_signal(137),
4261	grant(138) => grant_signal(138),
4262	grant(139) => grant_signal(139),
4263	grant(140) => grant_signal(140),
4264	grant(141) => grant_signal(141),
4265	grant(142) => grant_signal(142),
4266	grant(143) => grant_signal(143),
4267	grant(144) => grant_signal(144),
4268	grant(145) => grant_signal(145),
4269	grant(146) => grant_signal(146),
4270	grant(147) => grant_signal(147),
4271	grant(148) => grant_signal(148),
4272	grant(149) => grant_signal(149),
4273	grant(150) => grant_signal(150),
4274	fifo_full =>fifo_in_full(10),
4275	priority_rotation => priority_rotation_signal(10),
4276	fifo_empty => fifo_in_empty(10),
4277	data_out =>crossbar_in_port10,
4278	data_out_pulse =>crossbar_in_pulse10,
4279	request(136) =>request_signal(136),
4280	request(137) =>request_signal(137),
4281	request(138) =>request_signal(138),
4282	request(139) =>request_signal(139),
4283	request(140) =>request_signal(140),
4284	request(141) =>request_signal(141),
4285	request(142) =>request_signal(142),
4286	request(143) =>request_signal(143),
4287	request(144) =>request_signal(144),
4288	request(145) =>request_signal(145),
4289	request(146) =>request_signal(146),
4290	request(147) =>request_signal(147),
4291	request(148) =>request_signal(148),
4292	request(149) =>request_signal(149),
4293	request(150) =>request_signal(150)
4294	);
4295
4296	PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4297	GENERIC MAP(number_of_ports =>15)
4298	PORT MAP(
4299	data_in => Port11_in,
4300	data_in_en => data_in_en(11),
4301	reset => reset,
4302	clk =>clk,
4303	grant(151) => grant_signal(151),
4304	grant(152) => grant_signal(152),
4305	grant(153) => grant_signal(153),
4306	grant(154) => grant_signal(154),
4307	grant(155) => grant_signal(155),
4308	grant(156) => grant_signal(156),
4309	grant(157) => grant_signal(157),
4310	grant(158) => grant_signal(158),
4311	grant(159) => grant_signal(159),
4312	grant(160) => grant_signal(160),
4313	grant(161) => grant_signal(161),
4314	grant(162) => grant_signal(162),
4315	grant(163) => grant_signal(163),
4316	grant(164) => grant_signal(164),
4317	grant(165) => grant_signal(165),
4318	fifo_full =>fifo_in_full(11),
4319	priority_rotation => priority_rotation_signal(11),
4320	fifo_empty => fifo_in_empty(11),
4321	data_out =>crossbar_in_port11,
4322	data_out_pulse =>crossbar_in_pulse11,
4323	request(151) =>request_signal(151),
4324	request(152) =>request_signal(152),
4325	request(153) =>request_signal(153),
4326	request(154) =>request_signal(154),
4327	request(155) =>request_signal(155),
4328	request(156) =>request_signal(156),
4329	request(157) =>request_signal(157),
4330	request(158) =>request_signal(158),
4331	request(159) =>request_signal(159),
4332	request(160) =>request_signal(160),
4333	request(161) =>request_signal(161),
4334	request(162) =>request_signal(162),
4335	request(163) =>request_signal(163),
4336	request(164) =>request_signal(164),
4337	request(165) =>request_signal(165)
4338	);
4339
4340	PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4341	GENERIC MAP(number_of_ports =>15)
4342	PORT MAP(
4343	data_in => Port12_in,
4344	data_in_en => data_in_en(12),
4345	reset => reset,
4346	clk =>clk,
4347	grant(166) => grant_signal(166),
4348	grant(167) => grant_signal(167),
4349	grant(168) => grant_signal(168),
4350	grant(169) => grant_signal(169),
4351	grant(170) => grant_signal(170),
4352	grant(171) => grant_signal(171),
4353	grant(172) => grant_signal(172),
4354	grant(173) => grant_signal(173),
4355	grant(174) => grant_signal(174),
4356	grant(175) => grant_signal(175),
4357	grant(176) => grant_signal(176),
4358	grant(177) => grant_signal(177),
4359	grant(178) => grant_signal(178),
4360	grant(179) => grant_signal(179),
4361	grant(180) => grant_signal(180),
4362	fifo_full =>fifo_in_full(12),
4363	priority_rotation => priority_rotation_signal(12),
4364	fifo_empty => fifo_in_empty(12),
4365	data_out =>crossbar_in_port12,
4366	data_out_pulse =>crossbar_in_pulse12,
4367	request(166) =>request_signal(166),
4368	request(167) =>request_signal(167),
4369	request(168) =>request_signal(168),
4370	request(169) =>request_signal(169),
4371	request(170) =>request_signal(170),
4372	request(171) =>request_signal(171),
4373	request(172) =>request_signal(172),
4374	request(173) =>request_signal(173),
4375	request(174) =>request_signal(174),
4376	request(175) =>request_signal(175),
4377	request(176) =>request_signal(176),
4378	request(177) =>request_signal(177),
4379	request(178) =>request_signal(178),
4380	request(179) =>request_signal(179),
4381	request(180) =>request_signal(180)
4382	);
4383
4384	PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4385	GENERIC MAP(number_of_ports =>15)
4386	PORT MAP(
4387	data_in => Port13_in,
4388	data_in_en => data_in_en(13),
4389	reset => reset,
4390	clk =>clk,
4391	grant(181) => grant_signal(181),
4392	grant(182) => grant_signal(182),
4393	grant(183) => grant_signal(183),
4394	grant(184) => grant_signal(184),
4395	grant(185) => grant_signal(185),
4396	grant(186) => grant_signal(186),
4397	grant(187) => grant_signal(187),
4398	grant(188) => grant_signal(188),
4399	grant(189) => grant_signal(189),
4400	grant(190) => grant_signal(190),
4401	grant(191) => grant_signal(191),
4402	grant(192) => grant_signal(192),
4403	grant(193) => grant_signal(193),
4404	grant(194) => grant_signal(194),
4405	grant(195) => grant_signal(195),
4406	fifo_full =>fifo_in_full(13),
4407	priority_rotation => priority_rotation_signal(13),
4408	fifo_empty => fifo_in_empty(13),
4409	data_out =>crossbar_in_port13,
4410	data_out_pulse =>crossbar_in_pulse13,
4411	request(181) =>request_signal(181),
4412	request(182) =>request_signal(182),
4413	request(183) =>request_signal(183),
4414	request(184) =>request_signal(184),
4415	request(185) =>request_signal(185),
4416	request(186) =>request_signal(186),
4417	request(187) =>request_signal(187),
4418	request(188) =>request_signal(188),
4419	request(189) =>request_signal(189),
4420	request(190) =>request_signal(190),
4421	request(191) =>request_signal(191),
4422	request(192) =>request_signal(192),
4423	request(193) =>request_signal(193),
4424	request(194) =>request_signal(194),
4425	request(195) =>request_signal(195)
4426	);
4427
4428	PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4429	GENERIC MAP(number_of_ports =>15)
4430	PORT MAP(
4431	data_in => Port14_in,
4432	data_in_en => data_in_en(14),
4433	reset => reset,
4434	clk =>clk,
4435	grant(196) => grant_signal(196),
4436	grant(197) => grant_signal(197),
4437	grant(198) => grant_signal(198),
4438	grant(199) => grant_signal(199),
4439	grant(200) => grant_signal(200),
4440	grant(201) => grant_signal(201),
4441	grant(202) => grant_signal(202),
4442	grant(203) => grant_signal(203),
4443	grant(204) => grant_signal(204),
4444	grant(205) => grant_signal(205),
4445	grant(206) => grant_signal(206),
4446	grant(207) => grant_signal(207),
4447	grant(208) => grant_signal(208),
4448	grant(209) => grant_signal(209),
4449	grant(210) => grant_signal(210),
4450	fifo_full =>fifo_in_full(14),
4451	priority_rotation => priority_rotation_signal(14),
4452	fifo_empty => fifo_in_empty(14),
4453	data_out =>crossbar_in_port14,
4454	data_out_pulse =>crossbar_in_pulse14,
4455	request(196) =>request_signal(196),
4456	request(197) =>request_signal(197),
4457	request(198) =>request_signal(198),
4458	request(199) =>request_signal(199),
4459	request(200) =>request_signal(200),
4460	request(201) =>request_signal(201),
4461	request(202) =>request_signal(202),
4462	request(203) =>request_signal(203),
4463	request(204) =>request_signal(204),
4464	request(205) =>request_signal(205),
4465	request(206) =>request_signal(206),
4466	request(207) =>request_signal(207),
4467	request(208) =>request_signal(208),
4468	request(209) =>request_signal(209),
4469	request(210) =>request_signal(210)
4470	);
4471
4472	PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4473	GENERIC MAP(number_of_ports =>15)
4474	PORT MAP(
4475	data_in => Port15_in,
4476	data_in_en => data_in_en(15),
4477	reset => reset,
4478	clk =>clk,
4479	grant(211) => grant_signal(211),
4480	grant(212) => grant_signal(212),
4481	grant(213) => grant_signal(213),
4482	grant(214) => grant_signal(214),
4483	grant(215) => grant_signal(215),
4484	grant(216) => grant_signal(216),
4485	grant(217) => grant_signal(217),
4486	grant(218) => grant_signal(218),
4487	grant(219) => grant_signal(219),
4488	grant(220) => grant_signal(220),
4489	grant(221) => grant_signal(221),
4490	grant(222) => grant_signal(222),
4491	grant(223) => grant_signal(223),
4492	grant(224) => grant_signal(224),
4493	grant(225) => grant_signal(225),
4494	fifo_full =>fifo_in_full(15),
4495	priority_rotation => priority_rotation_signal(15),
4496	fifo_empty => fifo_in_empty(15),
4497	data_out =>crossbar_in_port15,
4498	data_out_pulse =>crossbar_in_pulse15,
4499	request(211) =>request_signal(211),
4500	request(212) =>request_signal(212),
4501	request(213) =>request_signal(213),
4502	request(214) =>request_signal(214),
4503	request(215) =>request_signal(215),
4504	request(216) =>request_signal(216),
4505	request(217) =>request_signal(217),
4506	request(218) =>request_signal(218),
4507	request(219) =>request_signal(219),
4508	request(220) =>request_signal(220),
4509	request(221) =>request_signal(221),
4510	request(222) =>request_signal(222),
4511	request(223) =>request_signal(223),
4512	request(224) =>request_signal(224),
4513	request(225) =>request_signal(225)
4514	);
4515
4516	end generate switch15x15;
4517
4518
4519	-- switch 16 ports
4520	switch16x16 : if number_of_ports = 16 generate
4521
4522	PORT1_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4523	GENERIC MAP(number_of_ports =>16)
4524	PORT MAP(
4525	data_in => Port1_in,
4526	data_in_en => data_in_en(1),
4527	reset => reset,
4528	clk =>clk,
4529	grant(1) => grant_signal(1),
4530	grant(2) => grant_signal(2),
4531	grant(3) => grant_signal(3),
4532	grant(4) => grant_signal(4),
4533	grant(5) => grant_signal(5),
4534	grant(6) => grant_signal(6),
4535	grant(7) => grant_signal(7),
4536	grant(8) => grant_signal(8),
4537	grant(9) => grant_signal(9),
4538	grant(10) => grant_signal(10),
4539	grant(11) => grant_signal(11),
4540	grant(12) => grant_signal(12),
4541	grant(13) => grant_signal(13),
4542	grant(14) => grant_signal(14),
4543	grant(15) => grant_signal(15),
4544	grant(16) => grant_signal(16),
4545	fifo_full =>fifo_in_full(1),
4546	priority_rotation => priority_rotation_signal(1),
4547	fifo_empty => fifo_in_empty(1),
4548	data_out =>crossbar_in_port1,
4549	data_out_pulse =>crossbar_in_pulse1,
4550	request(1) =>request_signal(1),
4551	request(2) =>request_signal(2),
4552	request(3) =>request_signal(3),
4553	request(4) =>request_signal(4),
4554	request(5) =>request_signal(5),
4555	request(6) =>request_signal(6),
4556	request(7) =>request_signal(7),
4557	request(8) =>request_signal(8),
4558	request(9) =>request_signal(9),
4559	request(10) =>request_signal(10),
4560	request(11) =>request_signal(11),
4561	request(12) =>request_signal(12),
4562	request(13) =>request_signal(13),
4563	request(14) =>request_signal(14),
4564	request(15) =>request_signal(15),
4565	request(16) =>request_signal(16)
4566	);
4567
4568	PORT2_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4569	GENERIC MAP(number_of_ports =>16)
4570	PORT MAP(
4571	data_in => Port2_in,
4572	data_in_en => data_in_en(2),
4573	reset => reset,
4574	clk =>clk,
4575	grant(17) => grant_signal(17),
4576	grant(18) => grant_signal(18),
4577	grant(19) => grant_signal(19),
4578	grant(20) => grant_signal(20),
4579	grant(21) => grant_signal(21),
4580	grant(22) => grant_signal(22),
4581	grant(23) => grant_signal(23),
4582	grant(24) => grant_signal(24),
4583	grant(25) => grant_signal(25),
4584	grant(26) => grant_signal(26),
4585	grant(27) => grant_signal(27),
4586	grant(28) => grant_signal(28),
4587	grant(29) => grant_signal(29),
4588	grant(30) => grant_signal(30),
4589	grant(31) => grant_signal(31),
4590	grant(32) => grant_signal(32),
4591	fifo_full =>fifo_in_full(2),
4592	priority_rotation => priority_rotation_signal(2),
4593	fifo_empty => fifo_in_empty(2),
4594	data_out =>crossbar_in_port2,
4595	data_out_pulse =>crossbar_in_pulse2,
4596	request(17) =>request_signal(17),
4597	request(18) =>request_signal(18),
4598	request(19) =>request_signal(19),
4599	request(20) =>request_signal(20),
4600	request(21) =>request_signal(21),
4601	request(22) =>request_signal(22),
4602	request(23) =>request_signal(23),
4603	request(24) =>request_signal(24),
4604	request(25) =>request_signal(25),
4605	request(26) =>request_signal(26),
4606	request(27) =>request_signal(27),
4607	request(28) =>request_signal(28),
4608	request(29) =>request_signal(29),
4609	request(30) =>request_signal(30),
4610	request(31) =>request_signal(31),
4611	request(32) =>request_signal(32)
4612	);
4613
4614	PORT3_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4615	GENERIC MAP(number_of_ports =>16)
4616	PORT MAP(
4617	data_in => Port3_in,
4618	data_in_en => data_in_en(3),
4619	reset => reset,
4620	clk =>clk,
4621	grant(33) => grant_signal(33),
4622	grant(34) => grant_signal(34),
4623	grant(35) => grant_signal(35),
4624	grant(36) => grant_signal(36),
4625	grant(37) => grant_signal(37),
4626	grant(38) => grant_signal(38),
4627	grant(39) => grant_signal(39),
4628	grant(40) => grant_signal(40),
4629	grant(41) => grant_signal(41),
4630	grant(42) => grant_signal(42),
4631	grant(43) => grant_signal(43),
4632	grant(44) => grant_signal(44),
4633	grant(45) => grant_signal(45),
4634	grant(46) => grant_signal(46),
4635	grant(47) => grant_signal(47),
4636	grant(48) => grant_signal(48),
4637	fifo_full =>fifo_in_full(3),
4638	priority_rotation => priority_rotation_signal(3),
4639	fifo_empty => fifo_in_empty(3),
4640	data_out =>crossbar_in_port3,
4641	data_out_pulse =>crossbar_in_pulse3,
4642	request(33) =>request_signal(33),
4643	request(34) =>request_signal(34),
4644	request(35) =>request_signal(35),
4645	request(36) =>request_signal(36),
4646	request(37) =>request_signal(37),
4647	request(38) =>request_signal(38),
4648	request(39) =>request_signal(39),
4649	request(40) =>request_signal(40),
4650	request(41) =>request_signal(41),
4651	request(42) =>request_signal(42),
4652	request(43) =>request_signal(43),
4653	request(44) =>request_signal(44),
4654	request(45) =>request_signal(45),
4655	request(46) =>request_signal(46),
4656	request(47) =>request_signal(47),
4657	request(48) =>request_signal(48)
4658	);
4659
4660	PORT4_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4661	GENERIC MAP(number_of_ports =>16)
4662	PORT MAP(
4663	data_in => Port4_in,
4664	data_in_en => data_in_en(4),
4665	reset => reset,
4666	clk =>clk,
4667	grant(49) => grant_signal(49),
4668	grant(50) => grant_signal(50),
4669	grant(51) => grant_signal(51),
4670	grant(52) => grant_signal(52),
4671	grant(53) => grant_signal(53),
4672	grant(54) => grant_signal(54),
4673	grant(55) => grant_signal(55),
4674	grant(56) => grant_signal(56),
4675	grant(57) => grant_signal(57),
4676	grant(58) => grant_signal(58),
4677	grant(59) => grant_signal(59),
4678	grant(60) => grant_signal(60),
4679	grant(61) => grant_signal(61),
4680	grant(62) => grant_signal(62),
4681	grant(63) => grant_signal(63),
4682	grant(64) => grant_signal(64),
4683	fifo_full =>fifo_in_full(4),
4684	priority_rotation => priority_rotation_signal(4),
4685	fifo_empty => fifo_in_empty(4),
4686	data_out =>crossbar_in_port4,
4687	data_out_pulse =>crossbar_in_pulse4,
4688	request(49) =>request_signal(49),
4689	request(50) =>request_signal(50),
4690	request(51) =>request_signal(51),
4691	request(52) =>request_signal(52),
4692	request(53) =>request_signal(53),
4693	request(54) =>request_signal(54),
4694	request(55) =>request_signal(55),
4695	request(56) =>request_signal(56),
4696	request(57) =>request_signal(57),
4697	request(58) =>request_signal(58),
4698	request(59) =>request_signal(59),
4699	request(60) =>request_signal(60),
4700	request(61) =>request_signal(61),
4701	request(62) =>request_signal(62),
4702	request(63) =>request_signal(63),
4703	request(64) =>request_signal(64)
4704	);
4705
4706	PORT5_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4707	GENERIC MAP(number_of_ports =>16)
4708	PORT MAP(
4709	data_in => Port5_in,
4710	data_in_en => data_in_en(5),
4711	reset => reset,
4712	clk =>clk,
4713	grant(65) => grant_signal(65),
4714	grant(66) => grant_signal(66),
4715	grant(67) => grant_signal(67),
4716	grant(68) => grant_signal(68),
4717	grant(69) => grant_signal(69),
4718	grant(70) => grant_signal(70),
4719	grant(71) => grant_signal(71),
4720	grant(72) => grant_signal(72),
4721	grant(73) => grant_signal(73),
4722	grant(74) => grant_signal(74),
4723	grant(75) => grant_signal(75),
4724	grant(76) => grant_signal(76),
4725	grant(77) => grant_signal(77),
4726	grant(78) => grant_signal(78),
4727	grant(79) => grant_signal(79),
4728	grant(80) => grant_signal(80),
4729	fifo_full =>fifo_in_full(5),
4730	priority_rotation => priority_rotation_signal(5),
4731	fifo_empty => fifo_in_empty(5),
4732	data_out =>crossbar_in_port5,
4733	data_out_pulse =>crossbar_in_pulse5,
4734	request(65) =>request_signal(65),
4735	request(66) =>request_signal(66),
4736	request(67) =>request_signal(67),
4737	request(68) =>request_signal(68),
4738	request(69) =>request_signal(69),
4739	request(70) =>request_signal(70),
4740	request(71) =>request_signal(71),
4741	request(72) =>request_signal(72),
4742	request(73) =>request_signal(73),
4743	request(74) =>request_signal(74),
4744	request(75) =>request_signal(75),
4745	request(76) =>request_signal(76),
4746	request(77) =>request_signal(77),
4747	request(78) =>request_signal(78),
4748	request(79) =>request_signal(79),
4749	request(80) =>request_signal(80)
4750	);
4751
4752	PORT6_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4753	GENERIC MAP(number_of_ports =>16)
4754	PORT MAP(
4755	data_in => Port6_in,
4756	data_in_en => data_in_en(6),
4757	reset => reset,
4758	clk =>clk,
4759	grant(81) => grant_signal(81),
4760	grant(82) => grant_signal(82),
4761	grant(83) => grant_signal(83),
4762	grant(84) => grant_signal(84),
4763	grant(85) => grant_signal(85),
4764	grant(86) => grant_signal(86),
4765	grant(87) => grant_signal(87),
4766	grant(88) => grant_signal(88),
4767	grant(89) => grant_signal(89),
4768	grant(90) => grant_signal(90),
4769	grant(91) => grant_signal(91),
4770	grant(92) => grant_signal(92),
4771	grant(93) => grant_signal(93),
4772	grant(94) => grant_signal(94),
4773	grant(95) => grant_signal(95),
4774	grant(96) => grant_signal(96),
4775	fifo_full =>fifo_in_full(6),
4776	priority_rotation => priority_rotation_signal(6),
4777	fifo_empty => fifo_in_empty(6),
4778	data_out =>crossbar_in_port6,
4779	data_out_pulse =>crossbar_in_pulse6,
4780	request(81) =>request_signal(81),
4781	request(82) =>request_signal(82),
4782	request(83) =>request_signal(83),
4783	request(84) =>request_signal(84),
4784	request(85) =>request_signal(85),
4785	request(86) =>request_signal(86),
4786	request(87) =>request_signal(87),
4787	request(88) =>request_signal(88),
4788	request(89) =>request_signal(89),
4789	request(90) =>request_signal(90),
4790	request(91) =>request_signal(91),
4791	request(92) =>request_signal(92),
4792	request(93) =>request_signal(93),
4793	request(94) =>request_signal(94),
4794	request(95) =>request_signal(95),
4795	request(96) =>request_signal(96)
4796	);
4797
4798	PORT7_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4799	GENERIC MAP(number_of_ports =>16)
4800	PORT MAP(
4801	data_in => Port7_in,
4802	data_in_en => data_in_en(7),
4803	reset => reset,
4804	clk =>clk,
4805	grant(97) => grant_signal(97),
4806	grant(98) => grant_signal(98),
4807	grant(99) => grant_signal(99),
4808	grant(100) => grant_signal(100),
4809	grant(101) => grant_signal(101),
4810	grant(102) => grant_signal(102),
4811	grant(103) => grant_signal(103),
4812	grant(104) => grant_signal(104),
4813	grant(105) => grant_signal(105),
4814	grant(106) => grant_signal(106),
4815	grant(107) => grant_signal(107),
4816	grant(108) => grant_signal(108),
4817	grant(109) => grant_signal(109),
4818	grant(110) => grant_signal(110),
4819	grant(111) => grant_signal(111),
4820	grant(112) => grant_signal(112),
4821	fifo_full =>fifo_in_full(7),
4822	priority_rotation => priority_rotation_signal(7),
4823	fifo_empty => fifo_in_empty(7),
4824	data_out =>crossbar_in_port7,
4825	data_out_pulse =>crossbar_in_pulse7,
4826	request(97) =>request_signal(97),
4827	request(98) =>request_signal(98),
4828	request(99) =>request_signal(99),
4829	request(100) =>request_signal(100),
4830	request(101) =>request_signal(101),
4831	request(102) =>request_signal(102),
4832	request(103) =>request_signal(103),
4833	request(104) =>request_signal(104),
4834	request(105) =>request_signal(105),
4835	request(106) =>request_signal(106),
4836	request(107) =>request_signal(107),
4837	request(108) =>request_signal(108),
4838	request(109) =>request_signal(109),
4839	request(110) =>request_signal(110),
4840	request(111) =>request_signal(111),
4841	request(112) =>request_signal(112)
4842	);
4843
4844	PORT8_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4845	GENERIC MAP(number_of_ports =>16)
4846	PORT MAP(
4847	data_in => Port8_in,
4848	data_in_en => data_in_en(8),
4849	reset => reset,
4850	clk =>clk,
4851	grant(113) => grant_signal(113),
4852	grant(114) => grant_signal(114),
4853	grant(115) => grant_signal(115),
4854	grant(116) => grant_signal(116),
4855	grant(117) => grant_signal(117),
4856	grant(118) => grant_signal(118),
4857	grant(119) => grant_signal(119),
4858	grant(120) => grant_signal(120),
4859	grant(121) => grant_signal(121),
4860	grant(122) => grant_signal(122),
4861	grant(123) => grant_signal(123),
4862	grant(124) => grant_signal(124),
4863	grant(125) => grant_signal(125),
4864	grant(126) => grant_signal(126),
4865	grant(127) => grant_signal(127),
4866	grant(128) => grant_signal(128),
4867	fifo_full =>fifo_in_full(8),
4868	priority_rotation => priority_rotation_signal(8),
4869	fifo_empty => fifo_in_empty(8),
4870	data_out =>crossbar_in_port8,
4871	data_out_pulse =>crossbar_in_pulse8,
4872	request(113) =>request_signal(113),
4873	request(114) =>request_signal(114),
4874	request(115) =>request_signal(115),
4875	request(116) =>request_signal(116),
4876	request(117) =>request_signal(117),
4877	request(118) =>request_signal(118),
4878	request(119) =>request_signal(119),
4879	request(120) =>request_signal(120),
4880	request(121) =>request_signal(121),
4881	request(122) =>request_signal(122),
4882	request(123) =>request_signal(123),
4883	request(124) =>request_signal(124),
4884	request(125) =>request_signal(125),
4885	request(126) =>request_signal(126),
4886	request(127) =>request_signal(127),
4887	request(128) =>request_signal(128)
4888	);
4889
4890	PORT9_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4891	GENERIC MAP(number_of_ports =>16)
4892	PORT MAP(
4893	data_in => Port9_in,
4894	data_in_en => data_in_en(9),
4895	reset => reset,
4896	clk =>clk,
4897	grant(129) => grant_signal(129),
4898	grant(130) => grant_signal(130),
4899	grant(131) => grant_signal(131),
4900	grant(132) => grant_signal(132),
4901	grant(133) => grant_signal(133),
4902	grant(134) => grant_signal(134),
4903	grant(135) => grant_signal(135),
4904	grant(136) => grant_signal(136),
4905	grant(137) => grant_signal(137),
4906	grant(138) => grant_signal(138),
4907	grant(139) => grant_signal(139),
4908	grant(140) => grant_signal(140),
4909	grant(141) => grant_signal(141),
4910	grant(142) => grant_signal(142),
4911	grant(143) => grant_signal(143),
4912	grant(144) => grant_signal(144),
4913	fifo_full =>fifo_in_full(9),
4914	priority_rotation => priority_rotation_signal(9),
4915	fifo_empty => fifo_in_empty(9),
4916	data_out =>crossbar_in_port9,
4917	data_out_pulse =>crossbar_in_pulse9,
4918	request(129) =>request_signal(129),
4919	request(130) =>request_signal(130),
4920	request(131) =>request_signal(131),
4921	request(132) =>request_signal(132),
4922	request(133) =>request_signal(133),
4923	request(134) =>request_signal(134),
4924	request(135) =>request_signal(135),
4925	request(136) =>request_signal(136),
4926	request(137) =>request_signal(137),
4927	request(138) =>request_signal(138),
4928	request(139) =>request_signal(139),
4929	request(140) =>request_signal(140),
4930	request(141) =>request_signal(141),
4931	request(142) =>request_signal(142),
4932	request(143) =>request_signal(143),
4933	request(144) =>request_signal(144)
4934	);
4935
4936	PORT10_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4937	GENERIC MAP(number_of_ports =>16)
4938	PORT MAP(
4939	data_in => Port10_in,
4940	data_in_en => data_in_en(10),
4941	reset => reset,
4942	clk =>clk,
4943	grant(145) => grant_signal(145),
4944	grant(146) => grant_signal(146),
4945	grant(147) => grant_signal(147),
4946	grant(148) => grant_signal(148),
4947	grant(149) => grant_signal(149),
4948	grant(150) => grant_signal(150),
4949	grant(151) => grant_signal(151),
4950	grant(152) => grant_signal(152),
4951	grant(153) => grant_signal(153),
4952	grant(154) => grant_signal(154),
4953	grant(155) => grant_signal(155),
4954	grant(156) => grant_signal(156),
4955	grant(157) => grant_signal(157),
4956	grant(158) => grant_signal(158),
4957	grant(159) => grant_signal(159),
4958	grant(160) => grant_signal(160),
4959	fifo_full =>fifo_in_full(10),
4960	priority_rotation => priority_rotation_signal(10),
4961	fifo_empty => fifo_in_empty(10),
4962	data_out =>crossbar_in_port10,
4963	data_out_pulse =>crossbar_in_pulse10,
4964	request(145) =>request_signal(145),
4965	request(146) =>request_signal(146),
4966	request(147) =>request_signal(147),
4967	request(148) =>request_signal(148),
4968	request(149) =>request_signal(149),
4969	request(150) =>request_signal(150),
4970	request(151) =>request_signal(151),
4971	request(152) =>request_signal(152),
4972	request(153) =>request_signal(153),
4973	request(154) =>request_signal(154),
4974	request(155) =>request_signal(155),
4975	request(156) =>request_signal(156),
4976	request(157) =>request_signal(157),
4977	request(158) =>request_signal(158),
4978	request(159) =>request_signal(159),
4979	request(160) =>request_signal(160)
4980	);
4981
4982	PORT11_INPUT_PORT_MODULE: INPUT_PORT_MODULE
4983	GENERIC MAP(number_of_ports =>16)
4984	PORT MAP(
4985	data_in => Port11_in,
4986	data_in_en => data_in_en(11),
4987	reset => reset,
4988	clk =>clk,
4989	grant(161) => grant_signal(161),
4990	grant(162) => grant_signal(162),
4991	grant(163) => grant_signal(163),
4992	grant(164) => grant_signal(164),
4993	grant(165) => grant_signal(165),
4994	grant(166) => grant_signal(166),
4995	grant(167) => grant_signal(167),
4996	grant(168) => grant_signal(168),
4997	grant(169) => grant_signal(169),
4998	grant(170) => grant_signal(170),
4999	grant(171) => grant_signal(171),
5000	grant(172) => grant_signal(172),
5001	grant(173) => grant_signal(173),
5002	grant(174) => grant_signal(174),
5003	grant(175) => grant_signal(175),
5004	grant(176) => grant_signal(176),
5005	fifo_full =>fifo_in_full(11),
5006	priority_rotation => priority_rotation_signal(11),
5007	fifo_empty => fifo_in_empty(11),
5008	data_out =>crossbar_in_port11,
5009	data_out_pulse =>crossbar_in_pulse11,
5010	request(161) =>request_signal(161),
5011	request(162) =>request_signal(162),
5012	request(163) =>request_signal(163),
5013	request(164) =>request_signal(164),
5014	request(165) =>request_signal(165),
5015	request(166) =>request_signal(166),
5016	request(167) =>request_signal(167),
5017	request(168) =>request_signal(168),
5018	request(169) =>request_signal(169),
5019	request(170) =>request_signal(170),
5020	request(171) =>request_signal(171),
5021	request(172) =>request_signal(172),
5022	request(173) =>request_signal(173),
5023	request(174) =>request_signal(174),
5024	request(175) =>request_signal(175),
5025	request(176) =>request_signal(176)
5026	);
5027
5028	PORT12_INPUT_PORT_MODULE: INPUT_PORT_MODULE
5029	GENERIC MAP(number_of_ports =>16)
5030	PORT MAP(
5031	data_in => Port12_in,
5032	data_in_en => data_in_en(12),
5033	reset => reset,
5034	clk =>clk,
5035	grant(177) => grant_signal(177),
5036	grant(178) => grant_signal(178),
5037	grant(179) => grant_signal(179),
5038	grant(180) => grant_signal(180),
5039	grant(181) => grant_signal(181),
5040	grant(182) => grant_signal(182),
5041	grant(183) => grant_signal(183),
5042	grant(184) => grant_signal(184),
5043	grant(185) => grant_signal(185),
5044	grant(186) => grant_signal(186),
5045	grant(187) => grant_signal(187),
5046	grant(188) => grant_signal(188),
5047	grant(189) => grant_signal(189),
5048	grant(190) => grant_signal(190),
5049	grant(191) => grant_signal(191),
5050	grant(192) => grant_signal(192),
5051	fifo_full =>fifo_in_full(12),
5052	priority_rotation => priority_rotation_signal(12),
5053	fifo_empty => fifo_in_empty(12),
5054	data_out =>crossbar_in_port12,
5055	data_out_pulse =>crossbar_in_pulse12,
5056	request(177) =>request_signal(177),
5057	request(178) =>request_signal(178),
5058	request(179) =>request_signal(179),
5059	request(180) =>request_signal(180),
5060	request(181) =>request_signal(181),
5061	request(182) =>request_signal(182),
5062	request(183) =>request_signal(183),
5063	request(184) =>request_signal(184),
5064	request(185) =>request_signal(185),
5065	request(186) =>request_signal(186),
5066	request(187) =>request_signal(187),
5067	request(188) =>request_signal(188),
5068	request(189) =>request_signal(189),
5069	request(190) =>request_signal(190),
5070	request(191) =>request_signal(191),
5071	request(192) =>request_signal(192)
5072	);
5073
5074	PORT13_INPUT_PORT_MODULE: INPUT_PORT_MODULE
5075	GENERIC MAP(number_of_ports =>16)
5076	PORT MAP(
5077	data_in => Port13_in,
5078	data_in_en => data_in_en(13),
5079	reset => reset,
5080	clk =>clk,
5081	grant(193) => grant_signal(193),
5082	grant(194) => grant_signal(194),
5083	grant(195) => grant_signal(195),
5084	grant(196) => grant_signal(196),
5085	grant(197) => grant_signal(197),
5086	grant(198) => grant_signal(198),
5087	grant(199) => grant_signal(199),
5088	grant(200) => grant_signal(200),
5089	grant(201) => grant_signal(201),
5090	grant(202) => grant_signal(202),
5091	grant(203) => grant_signal(203),
5092	grant(204) => grant_signal(204),
5093	grant(205) => grant_signal(205),
5094	grant(206) => grant_signal(206),
5095	grant(207) => grant_signal(207),
5096	grant(208) => grant_signal(208),
5097	fifo_full =>fifo_in_full(13),
5098	priority_rotation => priority_rotation_signal(13),
5099	fifo_empty => fifo_in_empty(13),
5100	data_out =>crossbar_in_port13,
5101	data_out_pulse =>crossbar_in_pulse13,
5102	request(193) =>request_signal(193),
5103	request(194) =>request_signal(194),
5104	request(195) =>request_signal(195),
5105	request(196) =>request_signal(196),
5106	request(197) =>request_signal(197),
5107	request(198) =>request_signal(198),
5108	request(199) =>request_signal(199),
5109	request(200) =>request_signal(200),
5110	request(201) =>request_signal(201),
5111	request(202) =>request_signal(202),
5112	request(203) =>request_signal(203),
5113	request(204) =>request_signal(204),
5114	request(205) =>request_signal(205),
5115	request(206) =>request_signal(206),
5116	request(207) =>request_signal(207),
5117	request(208) =>request_signal(208)
5118	);
5119
5120	PORT14_INPUT_PORT_MODULE: INPUT_PORT_MODULE
5121	GENERIC MAP(number_of_ports =>16)
5122	PORT MAP(
5123	data_in => Port14_in,
5124	data_in_en => data_in_en(14),
5125	reset => reset,
5126	clk =>clk,
5127	grant(209) => grant_signal(209),
5128	grant(210) => grant_signal(210),
5129	grant(211) => grant_signal(211),
5130	grant(212) => grant_signal(212),
5131	grant(213) => grant_signal(213),
5132	grant(214) => grant_signal(214),
5133	grant(215) => grant_signal(215),
5134	grant(216) => grant_signal(216),
5135	grant(217) => grant_signal(217),
5136	grant(218) => grant_signal(218),
5137	grant(219) => grant_signal(219),
5138	grant(220) => grant_signal(220),
5139	grant(221) => grant_signal(221),
5140	grant(222) => grant_signal(222),
5141	grant(223) => grant_signal(223),
5142	grant(224) => grant_signal(224),
5143	fifo_full =>fifo_in_full(14),
5144	priority_rotation => priority_rotation_signal(14),
5145	fifo_empty => fifo_in_empty(14),
5146	data_out =>crossbar_in_port14,
5147	data_out_pulse =>crossbar_in_pulse14,
5148	request(209) =>request_signal(209),
5149	request(210) =>request_signal(210),
5150	request(211) =>request_signal(211),
5151	request(212) =>request_signal(212),
5152	request(213) =>request_signal(213),
5153	request(214) =>request_signal(214),
5154	request(215) =>request_signal(215),
5155	request(216) =>request_signal(216),
5156	request(217) =>request_signal(217),
5157	request(218) =>request_signal(218),
5158	request(219) =>request_signal(219),
5159	request(220) =>request_signal(220),
5160	request(221) =>request_signal(221),
5161	request(222) =>request_signal(222),
5162	request(223) =>request_signal(223),
5163	request(224) =>request_signal(224)
5164	);
5165
5166	PORT15_INPUT_PORT_MODULE: INPUT_PORT_MODULE
5167	GENERIC MAP(number_of_ports =>16)
5168	PORT MAP(
5169	data_in => Port15_in,
5170	data_in_en => data_in_en(15),
5171	reset => reset,
5172	clk =>clk,
5173	grant(225) => grant_signal(225),
5174	grant(226) => grant_signal(226),
5175	grant(227) => grant_signal(227),
5176	grant(228) => grant_signal(228),
5177	grant(229) => grant_signal(229),
5178	grant(230) => grant_signal(230),
5179	grant(231) => grant_signal(231),
5180	grant(232) => grant_signal(232),
5181	grant(233) => grant_signal(233),
5182	grant(234) => grant_signal(234),
5183	grant(235) => grant_signal(235),
5184	grant(236) => grant_signal(236),
5185	grant(237) => grant_signal(237),
5186	grant(238) => grant_signal(238),
5187	grant(239) => grant_signal(239),
5188	grant(240) => grant_signal(240),
5189	fifo_full =>fifo_in_full(15),
5190	priority_rotation => priority_rotation_signal(15),
5191	fifo_empty => fifo_in_empty(15),
5192	data_out =>crossbar_in_port15,
5193	data_out_pulse =>crossbar_in_pulse15,
5194	request(225) =>request_signal(225),
5195	request(226) =>request_signal(226),
5196	request(227) =>request_signal(227),
5197	request(228) =>request_signal(228),
5198	request(229) =>request_signal(229),
5199	request(230) =>request_signal(230),
5200	request(231) =>request_signal(231),
5201	request(232) =>request_signal(232),
5202	request(233) =>request_signal(233),
5203	request(234) =>request_signal(234),
5204	request(235) =>request_signal(235),
5205	request(236) =>request_signal(236),
5206	request(237) =>request_signal(237),
5207	request(238) =>request_signal(238),
5208	request(239) =>request_signal(239),
5209	request(240) =>request_signal(240)
5210	);
5211
5212	PORT16_INPUT_PORT_MODULE: INPUT_PORT_MODULE
5213	GENERIC MAP(number_of_ports =>16)
5214	PORT MAP(
5215	data_in => Port16_in,
5216	data_in_en => data_in_en(16),
5217	reset => reset,
5218	clk =>clk,
5219	grant(241) => grant_signal(241),
5220	grant(242) => grant_signal(242),
5221	grant(243) => grant_signal(243),
5222	grant(244) => grant_signal(244),
5223	grant(245) => grant_signal(245),
5224	grant(246) => grant_signal(246),
5225	grant(247) => grant_signal(247),
5226	grant(248) => grant_signal(248),
5227	grant(249) => grant_signal(249),
5228	grant(250) => grant_signal(250),
5229	grant(251) => grant_signal(251),
5230	grant(252) => grant_signal(252),
5231	grant(253) => grant_signal(253),
5232	grant(254) => grant_signal(254),
5233	grant(255) => grant_signal(255),
5234	grant(256) => grant_signal(256),
5235	fifo_full =>fifo_in_full(16),
5236	priority_rotation => priority_rotation_signal(16),
5237	fifo_empty => fifo_in_empty(16),
5238	data_out =>crossbar_in_port16,
5239	data_out_pulse =>crossbar_in_pulse16,
5240	request(241) =>request_signal(241),
5241	request(242) =>request_signal(242),
5242	request(243) =>request_signal(243),
5243	request(244) =>request_signal(244),
5244	request(245) =>request_signal(245),
5245	request(246) =>request_signal(246),
5246	request(247) =>request_signal(247),
5247	request(248) =>request_signal(248),
5248	request(249) =>request_signal(249),
5249	request(250) =>request_signal(250),
5250	request(251) =>request_signal(251),
5251	request(252) =>request_signal(252),
5252	request(253) =>request_signal(253),
5253	request(254) =>request_signal(254),
5254	request(255) =>request_signal(255),
5255	request(256) =>request_signal(256)
5256	);
5257
5258	end generate switch16x16;
5259	-- intstanciation et connexion des modules des ports de sorties fonction du nombre de ports
5260	-- le circuit genere depend du parametre generique nombre de ports
5261	-- switch 2 ports
5262	port_out_switch2x2 : if number_of_ports = 2 generate
5263
5264	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5265	PORT MAP(
5266	data_in => crossbar_out_port1,
5267	reset => reset,
5268	clk => clk,
5269	wr_en =>crossbar_out_pulse1,
5270	data_out =>Port1_out,
5271	fifo_full =>fifo_out_full_signal(1),
5272	data_avalaible => data_available(1),
5273	rd_out_en => data_out_en(1)
5274	);
5275
5276	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5277	PORT MAP(
5278	data_in => crossbar_out_port2,
5279	reset => reset,
5280	clk => clk,
5281	wr_en =>crossbar_out_pulse2,
5282	data_out =>Port2_out,
5283	fifo_full =>fifo_out_full_signal(2),
5284	data_avalaible => data_available(2),
5285	rd_out_en => data_out_en(2)
5286	);
5287
5288	end generate port_out_switch2x2;
5289
5290
5291	-- switch 3 ports
5292	port_out_switch3x3 : if number_of_ports = 3 generate
5293
5294	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5295	PORT MAP(
5296	data_in => crossbar_out_port1,
5297	reset => reset,
5298	clk => clk,
5299	wr_en =>crossbar_out_pulse1,
5300	data_out =>Port1_out,
5301	fifo_full =>fifo_out_full_signal(1),
5302	data_avalaible => data_available(1),
5303	rd_out_en => data_out_en(1)
5304	);
5305
5306	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5307	PORT MAP(
5308	data_in => crossbar_out_port2,
5309	reset => reset,
5310	clk => clk,
5311	wr_en =>crossbar_out_pulse2,
5312	data_out =>Port2_out,
5313	fifo_full =>fifo_out_full_signal(2),
5314	data_avalaible => data_available(2),
5315	rd_out_en => data_out_en(2)
5316	);
5317
5318	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5319	PORT MAP(
5320	data_in => crossbar_out_port3,
5321	reset => reset,
5322	clk => clk,
5323	wr_en =>crossbar_out_pulse3,
5324	data_out =>Port3_out,
5325	fifo_full =>fifo_out_full_signal(3),
5326	data_avalaible => data_available(3),
5327	rd_out_en => data_out_en(3)
5328	);
5329
5330	end generate port_out_switch3x3;
5331
5332
5333	-- switch 4 ports
5334	port_out_switch4x4 : if number_of_ports = 4 generate
5335
5336	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5337	PORT MAP(
5338	data_in => crossbar_out_port1,
5339	reset => reset,
5340	clk => clk,
5341	wr_en =>crossbar_out_pulse1,
5342	data_out =>Port1_out,
5343	fifo_full =>fifo_out_full_signal(1),
5344	data_avalaible => data_available(1),
5345	rd_out_en => data_out_en(1)
5346	);
5347
5348	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5349	PORT MAP(
5350	data_in => crossbar_out_port2,
5351	reset => reset,
5352	clk => clk,
5353	wr_en =>crossbar_out_pulse2,
5354	data_out =>Port2_out,
5355	fifo_full =>fifo_out_full_signal(2),
5356	data_avalaible => data_available(2),
5357	rd_out_en => data_out_en(2)
5358	);
5359
5360	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5361	PORT MAP(
5362	data_in => crossbar_out_port3,
5363	reset => reset,
5364	clk => clk,
5365	wr_en =>crossbar_out_pulse3,
5366	data_out =>Port3_out,
5367	fifo_full =>fifo_out_full_signal(3),
5368	data_avalaible => data_available(3),
5369	rd_out_en => data_out_en(3)
5370	);
5371
5372	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5373	PORT MAP(
5374	data_in => crossbar_out_port4,
5375	reset => reset,
5376	clk => clk,
5377	wr_en =>crossbar_out_pulse4,
5378	data_out =>Port4_out,
5379	fifo_full =>fifo_out_full_signal(4),
5380	data_avalaible => data_available(4),
5381	rd_out_en => data_out_en(4)
5382	);
5383
5384	end generate port_out_switch4x4;
5385
5386
5387	-- switch 5 ports
5388	port_out_switch5x5 : if number_of_ports = 5 generate
5389
5390	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5391	PORT MAP(
5392	data_in => crossbar_out_port1,
5393	reset => reset,
5394	clk => clk,
5395	wr_en =>crossbar_out_pulse1,
5396	data_out =>Port1_out,
5397	fifo_full =>fifo_out_full_signal(1),
5398	data_avalaible => data_available(1),
5399	rd_out_en => data_out_en(1)
5400	);
5401
5402	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5403	PORT MAP(
5404	data_in => crossbar_out_port2,
5405	reset => reset,
5406	clk => clk,
5407	wr_en =>crossbar_out_pulse2,
5408	data_out =>Port2_out,
5409	fifo_full =>fifo_out_full_signal(2),
5410	data_avalaible => data_available(2),
5411	rd_out_en => data_out_en(2)
5412	);
5413
5414	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5415	PORT MAP(
5416	data_in => crossbar_out_port3,
5417	reset => reset,
5418	clk => clk,
5419	wr_en =>crossbar_out_pulse3,
5420	data_out =>Port3_out,
5421	fifo_full =>fifo_out_full_signal(3),
5422	data_avalaible => data_available(3),
5423	rd_out_en => data_out_en(3)
5424	);
5425
5426	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5427	PORT MAP(
5428	data_in => crossbar_out_port4,
5429	reset => reset,
5430	clk => clk,
5431	wr_en =>crossbar_out_pulse4,
5432	data_out =>Port4_out,
5433	fifo_full =>fifo_out_full_signal(4),
5434	data_avalaible => data_available(4),
5435	rd_out_en => data_out_en(4)
5436	);
5437
5438	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5439	PORT MAP(
5440	data_in => crossbar_out_port5,
5441	reset => reset,
5442	clk => clk,
5443	wr_en =>crossbar_out_pulse5,
5444	data_out =>Port5_out,
5445	fifo_full =>fifo_out_full_signal(5),
5446	data_avalaible => data_available(5),
5447	rd_out_en => data_out_en(5)
5448	);
5449
5450	end generate port_out_switch5x5;
5451
5452
5453	-- switch 6 ports
5454	port_out_switch6x6 : if number_of_ports = 6 generate
5455
5456	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5457	PORT MAP(
5458	data_in => crossbar_out_port1,
5459	reset => reset,
5460	clk => clk,
5461	wr_en =>crossbar_out_pulse1,
5462	data_out =>Port1_out,
5463	fifo_full =>fifo_out_full_signal(1),
5464	data_avalaible => data_available(1),
5465	rd_out_en => data_out_en(1)
5466	);
5467
5468	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5469	PORT MAP(
5470	data_in => crossbar_out_port2,
5471	reset => reset,
5472	clk => clk,
5473	wr_en =>crossbar_out_pulse2,
5474	data_out =>Port2_out,
5475	fifo_full =>fifo_out_full_signal(2),
5476	data_avalaible => data_available(2),
5477	rd_out_en => data_out_en(2)
5478	);
5479
5480	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5481	PORT MAP(
5482	data_in => crossbar_out_port3,
5483	reset => reset,
5484	clk => clk,
5485	wr_en =>crossbar_out_pulse3,
5486	data_out =>Port3_out,
5487	fifo_full =>fifo_out_full_signal(3),
5488	data_avalaible => data_available(3),
5489	rd_out_en => data_out_en(3)
5490	);
5491
5492	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5493	PORT MAP(
5494	data_in => crossbar_out_port4,
5495	reset => reset,
5496	clk => clk,
5497	wr_en =>crossbar_out_pulse4,
5498	data_out =>Port4_out,
5499	fifo_full =>fifo_out_full_signal(4),
5500	data_avalaible => data_available(4),
5501	rd_out_en => data_out_en(4)
5502	);
5503
5504	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5505	PORT MAP(
5506	data_in => crossbar_out_port5,
5507	reset => reset,
5508	clk => clk,
5509	wr_en =>crossbar_out_pulse5,
5510	data_out =>Port5_out,
5511	fifo_full =>fifo_out_full_signal(5),
5512	data_avalaible => data_available(5),
5513	rd_out_en => data_out_en(5)
5514	);
5515
5516	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5517	PORT MAP(
5518	data_in => crossbar_out_port6,
5519	reset => reset,
5520	clk => clk,
5521	wr_en =>crossbar_out_pulse6,
5522	data_out =>Port6_out,
5523	fifo_full =>fifo_out_full_signal(6),
5524	data_avalaible => data_available(6),
5525	rd_out_en => data_out_en(6)
5526	);
5527
5528	end generate port_out_switch6x6;
5529
5530
5531	-- switch 7 ports
5532	port_out_switch7x7 : if number_of_ports = 7 generate
5533
5534	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5535	PORT MAP(
5536	data_in => crossbar_out_port1,
5537	reset => reset,
5538	clk => clk,
5539	wr_en =>crossbar_out_pulse1,
5540	data_out =>Port1_out,
5541	fifo_full =>fifo_out_full_signal(1),
5542	data_avalaible => data_available(1),
5543	rd_out_en => data_out_en(1)
5544	);
5545
5546	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5547	PORT MAP(
5548	data_in => crossbar_out_port2,
5549	reset => reset,
5550	clk => clk,
5551	wr_en =>crossbar_out_pulse2,
5552	data_out =>Port2_out,
5553	fifo_full =>fifo_out_full_signal(2),
5554	data_avalaible => data_available(2),
5555	rd_out_en => data_out_en(2)
5556	);
5557
5558	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5559	PORT MAP(
5560	data_in => crossbar_out_port3,
5561	reset => reset,
5562	clk => clk,
5563	wr_en =>crossbar_out_pulse3,
5564	data_out =>Port3_out,
5565	fifo_full =>fifo_out_full_signal(3),
5566	data_avalaible => data_available(3),
5567	rd_out_en => data_out_en(3)
5568	);
5569
5570	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5571	PORT MAP(
5572	data_in => crossbar_out_port4,
5573	reset => reset,
5574	clk => clk,
5575	wr_en =>crossbar_out_pulse4,
5576	data_out =>Port4_out,
5577	fifo_full =>fifo_out_full_signal(4),
5578	data_avalaible => data_available(4),
5579	rd_out_en => data_out_en(4)
5580	);
5581
5582	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5583	PORT MAP(
5584	data_in => crossbar_out_port5,
5585	reset => reset,
5586	clk => clk,
5587	wr_en =>crossbar_out_pulse5,
5588	data_out =>Port5_out,
5589	fifo_full =>fifo_out_full_signal(5),
5590	data_avalaible => data_available(5),
5591	rd_out_en => data_out_en(5)
5592	);
5593
5594	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5595	PORT MAP(
5596	data_in => crossbar_out_port6,
5597	reset => reset,
5598	clk => clk,
5599	wr_en =>crossbar_out_pulse6,
5600	data_out =>Port6_out,
5601	fifo_full =>fifo_out_full_signal(6),
5602	data_avalaible => data_available(6),
5603	rd_out_en => data_out_en(6)
5604	);
5605
5606	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5607	PORT MAP(
5608	data_in => crossbar_out_port7,
5609	reset => reset,
5610	clk => clk,
5611	wr_en =>crossbar_out_pulse7,
5612	data_out =>Port7_out,
5613	fifo_full =>fifo_out_full_signal(7),
5614	data_avalaible => data_available(7),
5615	rd_out_en => data_out_en(7)
5616	);
5617
5618	end generate port_out_switch7x7;
5619
5620
5621	-- switch 8 ports
5622	port_out_switch8x8 : if number_of_ports = 8 generate
5623
5624	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5625	PORT MAP(
5626	data_in => crossbar_out_port1,
5627	reset => reset,
5628	clk => clk,
5629	wr_en =>crossbar_out_pulse1,
5630	data_out =>Port1_out,
5631	fifo_full =>fifo_out_full_signal(1),
5632	data_avalaible => data_available(1),
5633	rd_out_en => data_out_en(1)
5634	);
5635
5636	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5637	PORT MAP(
5638	data_in => crossbar_out_port2,
5639	reset => reset,
5640	clk => clk,
5641	wr_en =>crossbar_out_pulse2,
5642	data_out =>Port2_out,
5643	fifo_full =>fifo_out_full_signal(2),
5644	data_avalaible => data_available(2),
5645	rd_out_en => data_out_en(2)
5646	);
5647
5648	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5649	PORT MAP(
5650	data_in => crossbar_out_port3,
5651	reset => reset,
5652	clk => clk,
5653	wr_en =>crossbar_out_pulse3,
5654	data_out =>Port3_out,
5655	fifo_full =>fifo_out_full_signal(3),
5656	data_avalaible => data_available(3),
5657	rd_out_en => data_out_en(3)
5658	);
5659
5660	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5661	PORT MAP(
5662	data_in => crossbar_out_port4,
5663	reset => reset,
5664	clk => clk,
5665	wr_en =>crossbar_out_pulse4,
5666	data_out =>Port4_out,
5667	fifo_full =>fifo_out_full_signal(4),
5668	data_avalaible => data_available(4),
5669	rd_out_en => data_out_en(4)
5670	);
5671
5672	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5673	PORT MAP(
5674	data_in => crossbar_out_port5,
5675	reset => reset,
5676	clk => clk,
5677	wr_en =>crossbar_out_pulse5,
5678	data_out =>Port5_out,
5679	fifo_full =>fifo_out_full_signal(5),
5680	data_avalaible => data_available(5),
5681	rd_out_en => data_out_en(5)
5682	);
5683
5684	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5685	PORT MAP(
5686	data_in => crossbar_out_port6,
5687	reset => reset,
5688	clk => clk,
5689	wr_en =>crossbar_out_pulse6,
5690	data_out =>Port6_out,
5691	fifo_full =>fifo_out_full_signal(6),
5692	data_avalaible => data_available(6),
5693	rd_out_en => data_out_en(6)
5694	);
5695
5696	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5697	PORT MAP(
5698	data_in => crossbar_out_port7,
5699	reset => reset,
5700	clk => clk,
5701	wr_en =>crossbar_out_pulse7,
5702	data_out =>Port7_out,
5703	fifo_full =>fifo_out_full_signal(7),
5704	data_avalaible => data_available(7),
5705	rd_out_en => data_out_en(7)
5706	);
5707
5708	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5709	PORT MAP(
5710	data_in => crossbar_out_port8,
5711	reset => reset,
5712	clk => clk,
5713	wr_en =>crossbar_out_pulse8,
5714	data_out =>Port8_out,
5715	fifo_full =>fifo_out_full_signal(8),
5716	data_avalaible => data_available(8),
5717	rd_out_en => data_out_en(8)
5718	);
5719
5720	end generate port_out_switch8x8;
5721
5722
5723	-- switch 9 ports
5724	port_out_switch9x9 : if number_of_ports = 9 generate
5725
5726	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5727	PORT MAP(
5728	data_in => crossbar_out_port1,
5729	reset => reset,
5730	clk => clk,
5731	wr_en =>crossbar_out_pulse1,
5732	data_out =>Port1_out,
5733	fifo_full =>fifo_out_full_signal(1),
5734	data_avalaible => data_available(1),
5735	rd_out_en => data_out_en(1)
5736	);
5737
5738	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5739	PORT MAP(
5740	data_in => crossbar_out_port2,
5741	reset => reset,
5742	clk => clk,
5743	wr_en =>crossbar_out_pulse2,
5744	data_out =>Port2_out,
5745	fifo_full =>fifo_out_full_signal(2),
5746	data_avalaible => data_available(2),
5747	rd_out_en => data_out_en(2)
5748	);
5749
5750	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5751	PORT MAP(
5752	data_in => crossbar_out_port3,
5753	reset => reset,
5754	clk => clk,
5755	wr_en =>crossbar_out_pulse3,
5756	data_out =>Port3_out,
5757	fifo_full =>fifo_out_full_signal(3),
5758	data_avalaible => data_available(3),
5759	rd_out_en => data_out_en(3)
5760	);
5761
5762	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5763	PORT MAP(
5764	data_in => crossbar_out_port4,
5765	reset => reset,
5766	clk => clk,
5767	wr_en =>crossbar_out_pulse4,
5768	data_out =>Port4_out,
5769	fifo_full =>fifo_out_full_signal(4),
5770	data_avalaible => data_available(4),
5771	rd_out_en => data_out_en(4)
5772	);
5773
5774	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5775	PORT MAP(
5776	data_in => crossbar_out_port5,
5777	reset => reset,
5778	clk => clk,
5779	wr_en =>crossbar_out_pulse5,
5780	data_out =>Port5_out,
5781	fifo_full =>fifo_out_full_signal(5),
5782	data_avalaible => data_available(5),
5783	rd_out_en => data_out_en(5)
5784	);
5785
5786	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5787	PORT MAP(
5788	data_in => crossbar_out_port6,
5789	reset => reset,
5790	clk => clk,
5791	wr_en =>crossbar_out_pulse6,
5792	data_out =>Port6_out,
5793	fifo_full =>fifo_out_full_signal(6),
5794	data_avalaible => data_available(6),
5795	rd_out_en => data_out_en(6)
5796	);
5797
5798	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5799	PORT MAP(
5800	data_in => crossbar_out_port7,
5801	reset => reset,
5802	clk => clk,
5803	wr_en =>crossbar_out_pulse7,
5804	data_out =>Port7_out,
5805	fifo_full =>fifo_out_full_signal(7),
5806	data_avalaible => data_available(7),
5807	rd_out_en => data_out_en(7)
5808	);
5809
5810	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5811	PORT MAP(
5812	data_in => crossbar_out_port8,
5813	reset => reset,
5814	clk => clk,
5815	wr_en =>crossbar_out_pulse8,
5816	data_out =>Port8_out,
5817	fifo_full =>fifo_out_full_signal(8),
5818	data_avalaible => data_available(8),
5819	rd_out_en => data_out_en(8)
5820	);
5821
5822	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5823	PORT MAP(
5824	data_in => crossbar_out_port9,
5825	reset => reset,
5826	clk => clk,
5827	wr_en =>crossbar_out_pulse9,
5828	data_out =>Port9_out,
5829	fifo_full =>fifo_out_full_signal(9),
5830	data_avalaible => data_available(9),
5831	rd_out_en => data_out_en(9)
5832	);
5833
5834	end generate port_out_switch9x9;
5835
5836
5837	-- switch 10 ports
5838	port_out_switch10x10 : if number_of_ports = 10 generate
5839
5840	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5841	PORT MAP(
5842	data_in => crossbar_out_port1,
5843	reset => reset,
5844	clk => clk,
5845	wr_en =>crossbar_out_pulse1,
5846	data_out =>Port1_out,
5847	fifo_full =>fifo_out_full_signal(1),
5848	data_avalaible => data_available(1),
5849	rd_out_en => data_out_en(1)
5850	);
5851
5852	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5853	PORT MAP(
5854	data_in => crossbar_out_port2,
5855	reset => reset,
5856	clk => clk,
5857	wr_en =>crossbar_out_pulse2,
5858	data_out =>Port2_out,
5859	fifo_full =>fifo_out_full_signal(2),
5860	data_avalaible => data_available(2),
5861	rd_out_en => data_out_en(2)
5862	);
5863
5864	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5865	PORT MAP(
5866	data_in => crossbar_out_port3,
5867	reset => reset,
5868	clk => clk,
5869	wr_en =>crossbar_out_pulse3,
5870	data_out =>Port3_out,
5871	fifo_full =>fifo_out_full_signal(3),
5872	data_avalaible => data_available(3),
5873	rd_out_en => data_out_en(3)
5874	);
5875
5876	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5877	PORT MAP(
5878	data_in => crossbar_out_port4,
5879	reset => reset,
5880	clk => clk,
5881	wr_en =>crossbar_out_pulse4,
5882	data_out =>Port4_out,
5883	fifo_full =>fifo_out_full_signal(4),
5884	data_avalaible => data_available(4),
5885	rd_out_en => data_out_en(4)
5886	);
5887
5888	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5889	PORT MAP(
5890	data_in => crossbar_out_port5,
5891	reset => reset,
5892	clk => clk,
5893	wr_en =>crossbar_out_pulse5,
5894	data_out =>Port5_out,
5895	fifo_full =>fifo_out_full_signal(5),
5896	data_avalaible => data_available(5),
5897	rd_out_en => data_out_en(5)
5898	);
5899
5900	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5901	PORT MAP(
5902	data_in => crossbar_out_port6,
5903	reset => reset,
5904	clk => clk,
5905	wr_en =>crossbar_out_pulse6,
5906	data_out =>Port6_out,
5907	fifo_full =>fifo_out_full_signal(6),
5908	data_avalaible => data_available(6),
5909	rd_out_en => data_out_en(6)
5910	);
5911
5912	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5913	PORT MAP(
5914	data_in => crossbar_out_port7,
5915	reset => reset,
5916	clk => clk,
5917	wr_en =>crossbar_out_pulse7,
5918	data_out =>Port7_out,
5919	fifo_full =>fifo_out_full_signal(7),
5920	data_avalaible => data_available(7),
5921	rd_out_en => data_out_en(7)
5922	);
5923
5924	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5925	PORT MAP(
5926	data_in => crossbar_out_port8,
5927	reset => reset,
5928	clk => clk,
5929	wr_en =>crossbar_out_pulse8,
5930	data_out =>Port8_out,
5931	fifo_full =>fifo_out_full_signal(8),
5932	data_avalaible => data_available(8),
5933	rd_out_en => data_out_en(8)
5934	);
5935
5936	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5937	PORT MAP(
5938	data_in => crossbar_out_port9,
5939	reset => reset,
5940	clk => clk,
5941	wr_en =>crossbar_out_pulse9,
5942	data_out =>Port9_out,
5943	fifo_full =>fifo_out_full_signal(9),
5944	data_avalaible => data_available(9),
5945	rd_out_en => data_out_en(9)
5946	);
5947
5948	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5949	PORT MAP(
5950	data_in => crossbar_out_port10,
5951	reset => reset,
5952	clk => clk,
5953	wr_en =>crossbar_out_pulse10,
5954	data_out =>Port10_out,
5955	fifo_full =>fifo_out_full_signal(10),
5956	data_avalaible => data_available(10),
5957	rd_out_en => data_out_en(10)
5958	);
5959
5960	end generate port_out_switch10x10;
5961
5962
5963	-- switch 11 ports
5964	port_out_switch11x11 : if number_of_ports = 11 generate
5965
5966	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5967	PORT MAP(
5968	data_in => crossbar_out_port1,
5969	reset => reset,
5970	clk => clk,
5971	wr_en =>crossbar_out_pulse1,
5972	data_out =>Port1_out,
5973	fifo_full =>fifo_out_full_signal(1),
5974	data_avalaible => data_available(1),
5975	rd_out_en => data_out_en(1)
5976	);
5977
5978	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5979	PORT MAP(
5980	data_in => crossbar_out_port2,
5981	reset => reset,
5982	clk => clk,
5983	wr_en =>crossbar_out_pulse2,
5984	data_out =>Port2_out,
5985	fifo_full =>fifo_out_full_signal(2),
5986	data_avalaible => data_available(2),
5987	rd_out_en => data_out_en(2)
5988	);
5989
5990	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
5991	PORT MAP(
5992	data_in => crossbar_out_port3,
5993	reset => reset,
5994	clk => clk,
5995	wr_en =>crossbar_out_pulse3,
5996	data_out =>Port3_out,
5997	fifo_full =>fifo_out_full_signal(3),
5998	data_avalaible => data_available(3),
5999	rd_out_en => data_out_en(3)
6000	);
6001
6002	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6003	PORT MAP(
6004	data_in => crossbar_out_port4,
6005	reset => reset,
6006	clk => clk,
6007	wr_en =>crossbar_out_pulse4,
6008	data_out =>Port4_out,
6009	fifo_full =>fifo_out_full_signal(4),
6010	data_avalaible => data_available(4),
6011	rd_out_en => data_out_en(4)
6012	);
6013
6014	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6015	PORT MAP(
6016	data_in => crossbar_out_port5,
6017	reset => reset,
6018	clk => clk,
6019	wr_en =>crossbar_out_pulse5,
6020	data_out =>Port5_out,
6021	fifo_full =>fifo_out_full_signal(5),
6022	data_avalaible => data_available(5),
6023	rd_out_en => data_out_en(5)
6024	);
6025
6026	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6027	PORT MAP(
6028	data_in => crossbar_out_port6,
6029	reset => reset,
6030	clk => clk,
6031	wr_en =>crossbar_out_pulse6,
6032	data_out =>Port6_out,
6033	fifo_full =>fifo_out_full_signal(6),
6034	data_avalaible => data_available(6),
6035	rd_out_en => data_out_en(6)
6036	);
6037
6038	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6039	PORT MAP(
6040	data_in => crossbar_out_port7,
6041	reset => reset,
6042	clk => clk,
6043	wr_en =>crossbar_out_pulse7,
6044	data_out =>Port7_out,
6045	fifo_full =>fifo_out_full_signal(7),
6046	data_avalaible => data_available(7),
6047	rd_out_en => data_out_en(7)
6048	);
6049
6050	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6051	PORT MAP(
6052	data_in => crossbar_out_port8,
6053	reset => reset,
6054	clk => clk,
6055	wr_en =>crossbar_out_pulse8,
6056	data_out =>Port8_out,
6057	fifo_full =>fifo_out_full_signal(8),
6058	data_avalaible => data_available(8),
6059	rd_out_en => data_out_en(8)
6060	);
6061
6062	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6063	PORT MAP(
6064	data_in => crossbar_out_port9,
6065	reset => reset,
6066	clk => clk,
6067	wr_en =>crossbar_out_pulse9,
6068	data_out =>Port9_out,
6069	fifo_full =>fifo_out_full_signal(9),
6070	data_avalaible => data_available(9),
6071	rd_out_en => data_out_en(9)
6072	);
6073
6074	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6075	PORT MAP(
6076	data_in => crossbar_out_port10,
6077	reset => reset,
6078	clk => clk,
6079	wr_en =>crossbar_out_pulse10,
6080	data_out =>Port10_out,
6081	fifo_full =>fifo_out_full_signal(10),
6082	data_avalaible => data_available(10),
6083	rd_out_en => data_out_en(10)
6084	);
6085
6086	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6087	PORT MAP(
6088	data_in => crossbar_out_port11,
6089	reset => reset,
6090	clk => clk,
6091	wr_en =>crossbar_out_pulse11,
6092	data_out =>Port11_out,
6093	fifo_full =>fifo_out_full_signal(11),
6094	data_avalaible => data_available(11),
6095	rd_out_en => data_out_en(11)
6096	);
6097
6098	end generate port_out_switch11x11;
6099
6100
6101	-- switch 12 ports
6102	port_out_switch12x12 : if number_of_ports = 12 generate
6103
6104	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6105	PORT MAP(
6106	data_in => crossbar_out_port1,
6107	reset => reset,
6108	clk => clk,
6109	wr_en =>crossbar_out_pulse1,
6110	data_out =>Port1_out,
6111	fifo_full =>fifo_out_full_signal(1),
6112	data_avalaible => data_available(1),
6113	rd_out_en => data_out_en(1)
6114	);
6115
6116	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6117	PORT MAP(
6118	data_in => crossbar_out_port2,
6119	reset => reset,
6120	clk => clk,
6121	wr_en =>crossbar_out_pulse2,
6122	data_out =>Port2_out,
6123	fifo_full =>fifo_out_full_signal(2),
6124	data_avalaible => data_available(2),
6125	rd_out_en => data_out_en(2)
6126	);
6127
6128	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6129	PORT MAP(
6130	data_in => crossbar_out_port3,
6131	reset => reset,
6132	clk => clk,
6133	wr_en =>crossbar_out_pulse3,
6134	data_out =>Port3_out,
6135	fifo_full =>fifo_out_full_signal(3),
6136	data_avalaible => data_available(3),
6137	rd_out_en => data_out_en(3)
6138	);
6139
6140	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6141	PORT MAP(
6142	data_in => crossbar_out_port4,
6143	reset => reset,
6144	clk => clk,
6145	wr_en =>crossbar_out_pulse4,
6146	data_out =>Port4_out,
6147	fifo_full =>fifo_out_full_signal(4),
6148	data_avalaible => data_available(4),
6149	rd_out_en => data_out_en(4)
6150	);
6151
6152	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6153	PORT MAP(
6154	data_in => crossbar_out_port5,
6155	reset => reset,
6156	clk => clk,
6157	wr_en =>crossbar_out_pulse5,
6158	data_out =>Port5_out,
6159	fifo_full =>fifo_out_full_signal(5),
6160	data_avalaible => data_available(5),
6161	rd_out_en => data_out_en(5)
6162	);
6163
6164	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6165	PORT MAP(
6166	data_in => crossbar_out_port6,
6167	reset => reset,
6168	clk => clk,
6169	wr_en =>crossbar_out_pulse6,
6170	data_out =>Port6_out,
6171	fifo_full =>fifo_out_full_signal(6),
6172	data_avalaible => data_available(6),
6173	rd_out_en => data_out_en(6)
6174	);
6175
6176	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6177	PORT MAP(
6178	data_in => crossbar_out_port7,
6179	reset => reset,
6180	clk => clk,
6181	wr_en =>crossbar_out_pulse7,
6182	data_out =>Port7_out,
6183	fifo_full =>fifo_out_full_signal(7),
6184	data_avalaible => data_available(7),
6185	rd_out_en => data_out_en(7)
6186	);
6187
6188	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6189	PORT MAP(
6190	data_in => crossbar_out_port8,
6191	reset => reset,
6192	clk => clk,
6193	wr_en =>crossbar_out_pulse8,
6194	data_out =>Port8_out,
6195	fifo_full =>fifo_out_full_signal(8),
6196	data_avalaible => data_available(8),
6197	rd_out_en => data_out_en(8)
6198	);
6199
6200	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6201	PORT MAP(
6202	data_in => crossbar_out_port9,
6203	reset => reset,
6204	clk => clk,
6205	wr_en =>crossbar_out_pulse9,
6206	data_out =>Port9_out,
6207	fifo_full =>fifo_out_full_signal(9),
6208	data_avalaible => data_available(9),
6209	rd_out_en => data_out_en(9)
6210	);
6211
6212	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6213	PORT MAP(
6214	data_in => crossbar_out_port10,
6215	reset => reset,
6216	clk => clk,
6217	wr_en =>crossbar_out_pulse10,
6218	data_out =>Port10_out,
6219	fifo_full =>fifo_out_full_signal(10),
6220	data_avalaible => data_available(10),
6221	rd_out_en => data_out_en(10)
6222	);
6223
6224	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6225	PORT MAP(
6226	data_in => crossbar_out_port11,
6227	reset => reset,
6228	clk => clk,
6229	wr_en =>crossbar_out_pulse11,
6230	data_out =>Port11_out,
6231	fifo_full =>fifo_out_full_signal(11),
6232	data_avalaible => data_available(11),
6233	rd_out_en => data_out_en(11)
6234	);
6235
6236	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6237	PORT MAP(
6238	data_in => crossbar_out_port12,
6239	reset => reset,
6240	clk => clk,
6241	wr_en =>crossbar_out_pulse12,
6242	data_out =>Port12_out,
6243	fifo_full =>fifo_out_full_signal(12),
6244	data_avalaible => data_available(12),
6245	rd_out_en => data_out_en(12)
6246	);
6247
6248	end generate port_out_switch12x12;
6249
6250
6251	-- switch 13 ports
6252	port_out_switch13x13 : if number_of_ports = 13 generate
6253
6254	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6255	PORT MAP(
6256	data_in => crossbar_out_port1,
6257	reset => reset,
6258	clk => clk,
6259	wr_en =>crossbar_out_pulse1,
6260	data_out =>Port1_out,
6261	fifo_full =>fifo_out_full_signal(1),
6262	data_avalaible => data_available(1),
6263	rd_out_en => data_out_en(1)
6264	);
6265
6266	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6267	PORT MAP(
6268	data_in => crossbar_out_port2,
6269	reset => reset,
6270	clk => clk,
6271	wr_en =>crossbar_out_pulse2,
6272	data_out =>Port2_out,
6273	fifo_full =>fifo_out_full_signal(2),
6274	data_avalaible => data_available(2),
6275	rd_out_en => data_out_en(2)
6276	);
6277
6278	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6279	PORT MAP(
6280	data_in => crossbar_out_port3,
6281	reset => reset,
6282	clk => clk,
6283	wr_en =>crossbar_out_pulse3,
6284	data_out =>Port3_out,
6285	fifo_full =>fifo_out_full_signal(3),
6286	data_avalaible => data_available(3),
6287	rd_out_en => data_out_en(3)
6288	);
6289
6290	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6291	PORT MAP(
6292	data_in => crossbar_out_port4,
6293	reset => reset,
6294	clk => clk,
6295	wr_en =>crossbar_out_pulse4,
6296	data_out =>Port4_out,
6297	fifo_full =>fifo_out_full_signal(4),
6298	data_avalaible => data_available(4),
6299	rd_out_en => data_out_en(4)
6300	);
6301
6302	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6303	PORT MAP(
6304	data_in => crossbar_out_port5,
6305	reset => reset,
6306	clk => clk,
6307	wr_en =>crossbar_out_pulse5,
6308	data_out =>Port5_out,
6309	fifo_full =>fifo_out_full_signal(5),
6310	data_avalaible => data_available(5),
6311	rd_out_en => data_out_en(5)
6312	);
6313
6314	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6315	PORT MAP(
6316	data_in => crossbar_out_port6,
6317	reset => reset,
6318	clk => clk,
6319	wr_en =>crossbar_out_pulse6,
6320	data_out =>Port6_out,
6321	fifo_full =>fifo_out_full_signal(6),
6322	data_avalaible => data_available(6),
6323	rd_out_en => data_out_en(6)
6324	);
6325
6326	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6327	PORT MAP(
6328	data_in => crossbar_out_port7,
6329	reset => reset,
6330	clk => clk,
6331	wr_en =>crossbar_out_pulse7,
6332	data_out =>Port7_out,
6333	fifo_full =>fifo_out_full_signal(7),
6334	data_avalaible => data_available(7),
6335	rd_out_en => data_out_en(7)
6336	);
6337
6338	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6339	PORT MAP(
6340	data_in => crossbar_out_port8,
6341	reset => reset,
6342	clk => clk,
6343	wr_en =>crossbar_out_pulse8,
6344	data_out =>Port8_out,
6345	fifo_full =>fifo_out_full_signal(8),
6346	data_avalaible => data_available(8),
6347	rd_out_en => data_out_en(8)
6348	);
6349
6350	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6351	PORT MAP(
6352	data_in => crossbar_out_port9,
6353	reset => reset,
6354	clk => clk,
6355	wr_en =>crossbar_out_pulse9,
6356	data_out =>Port9_out,
6357	fifo_full =>fifo_out_full_signal(9),
6358	data_avalaible => data_available(9),
6359	rd_out_en => data_out_en(9)
6360	);
6361
6362	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6363	PORT MAP(
6364	data_in => crossbar_out_port10,
6365	reset => reset,
6366	clk => clk,
6367	wr_en =>crossbar_out_pulse10,
6368	data_out =>Port10_out,
6369	fifo_full =>fifo_out_full_signal(10),
6370	data_avalaible => data_available(10),
6371	rd_out_en => data_out_en(10)
6372	);
6373
6374	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6375	PORT MAP(
6376	data_in => crossbar_out_port11,
6377	reset => reset,
6378	clk => clk,
6379	wr_en =>crossbar_out_pulse11,
6380	data_out =>Port11_out,
6381	fifo_full =>fifo_out_full_signal(11),
6382	data_avalaible => data_available(11),
6383	rd_out_en => data_out_en(11)
6384	);
6385
6386	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6387	PORT MAP(
6388	data_in => crossbar_out_port12,
6389	reset => reset,
6390	clk => clk,
6391	wr_en =>crossbar_out_pulse12,
6392	data_out =>Port12_out,
6393	fifo_full =>fifo_out_full_signal(12),
6394	data_avalaible => data_available(12),
6395	rd_out_en => data_out_en(12)
6396	);
6397
6398	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6399	PORT MAP(
6400	data_in => crossbar_out_port13,
6401	reset => reset,
6402	clk => clk,
6403	wr_en =>crossbar_out_pulse13,
6404	data_out =>Port13_out,
6405	fifo_full =>fifo_out_full_signal(13),
6406	data_avalaible => data_available(13),
6407	rd_out_en => data_out_en(13)
6408	);
6409
6410	end generate port_out_switch13x13;
6411
6412
6413	-- switch 14 ports
6414	port_out_switch14x14 : if number_of_ports = 14 generate
6415
6416	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6417	PORT MAP(
6418	data_in => crossbar_out_port1,
6419	reset => reset,
6420	clk => clk,
6421	wr_en =>crossbar_out_pulse1,
6422	data_out =>Port1_out,
6423	fifo_full =>fifo_out_full_signal(1),
6424	data_avalaible => data_available(1),
6425	rd_out_en => data_out_en(1)
6426	);
6427
6428	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6429	PORT MAP(
6430	data_in => crossbar_out_port2,
6431	reset => reset,
6432	clk => clk,
6433	wr_en =>crossbar_out_pulse2,
6434	data_out =>Port2_out,
6435	fifo_full =>fifo_out_full_signal(2),
6436	data_avalaible => data_available(2),
6437	rd_out_en => data_out_en(2)
6438	);
6439
6440	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6441	PORT MAP(
6442	data_in => crossbar_out_port3,
6443	reset => reset,
6444	clk => clk,
6445	wr_en =>crossbar_out_pulse3,
6446	data_out =>Port3_out,
6447	fifo_full =>fifo_out_full_signal(3),
6448	data_avalaible => data_available(3),
6449	rd_out_en => data_out_en(3)
6450	);
6451
6452	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6453	PORT MAP(
6454	data_in => crossbar_out_port4,
6455	reset => reset,
6456	clk => clk,
6457	wr_en =>crossbar_out_pulse4,
6458	data_out =>Port4_out,
6459	fifo_full =>fifo_out_full_signal(4),
6460	data_avalaible => data_available(4),
6461	rd_out_en => data_out_en(4)
6462	);
6463
6464	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6465	PORT MAP(
6466	data_in => crossbar_out_port5,
6467	reset => reset,
6468	clk => clk,
6469	wr_en =>crossbar_out_pulse5,
6470	data_out =>Port5_out,
6471	fifo_full =>fifo_out_full_signal(5),
6472	data_avalaible => data_available(5),
6473	rd_out_en => data_out_en(5)
6474	);
6475
6476	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6477	PORT MAP(
6478	data_in => crossbar_out_port6,
6479	reset => reset,
6480	clk => clk,
6481	wr_en =>crossbar_out_pulse6,
6482	data_out =>Port6_out,
6483	fifo_full =>fifo_out_full_signal(6),
6484	data_avalaible => data_available(6),
6485	rd_out_en => data_out_en(6)
6486	);
6487
6488	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6489	PORT MAP(
6490	data_in => crossbar_out_port7,
6491	reset => reset,
6492	clk => clk,
6493	wr_en =>crossbar_out_pulse7,
6494	data_out =>Port7_out,
6495	fifo_full =>fifo_out_full_signal(7),
6496	data_avalaible => data_available(7),
6497	rd_out_en => data_out_en(7)
6498	);
6499
6500	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6501	PORT MAP(
6502	data_in => crossbar_out_port8,
6503	reset => reset,
6504	clk => clk,
6505	wr_en =>crossbar_out_pulse8,
6506	data_out =>Port8_out,
6507	fifo_full =>fifo_out_full_signal(8),
6508	data_avalaible => data_available(8),
6509	rd_out_en => data_out_en(8)
6510	);
6511
6512	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6513	PORT MAP(
6514	data_in => crossbar_out_port9,
6515	reset => reset,
6516	clk => clk,
6517	wr_en =>crossbar_out_pulse9,
6518	data_out =>Port9_out,
6519	fifo_full =>fifo_out_full_signal(9),
6520	data_avalaible => data_available(9),
6521	rd_out_en => data_out_en(9)
6522	);
6523
6524	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6525	PORT MAP(
6526	data_in => crossbar_out_port10,
6527	reset => reset,
6528	clk => clk,
6529	wr_en =>crossbar_out_pulse10,
6530	data_out =>Port10_out,
6531	fifo_full =>fifo_out_full_signal(10),
6532	data_avalaible => data_available(10),
6533	rd_out_en => data_out_en(10)
6534	);
6535
6536	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6537	PORT MAP(
6538	data_in => crossbar_out_port11,
6539	reset => reset,
6540	clk => clk,
6541	wr_en =>crossbar_out_pulse11,
6542	data_out =>Port11_out,
6543	fifo_full =>fifo_out_full_signal(11),
6544	data_avalaible => data_available(11),
6545	rd_out_en => data_out_en(11)
6546	);
6547
6548	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6549	PORT MAP(
6550	data_in => crossbar_out_port12,
6551	reset => reset,
6552	clk => clk,
6553	wr_en =>crossbar_out_pulse12,
6554	data_out =>Port12_out,
6555	fifo_full =>fifo_out_full_signal(12),
6556	data_avalaible => data_available(12),
6557	rd_out_en => data_out_en(12)
6558	);
6559
6560	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6561	PORT MAP(
6562	data_in => crossbar_out_port13,
6563	reset => reset,
6564	clk => clk,
6565	wr_en =>crossbar_out_pulse13,
6566	data_out =>Port13_out,
6567	fifo_full =>fifo_out_full_signal(13),
6568	data_avalaible => data_available(13),
6569	rd_out_en => data_out_en(13)
6570	);
6571
6572	PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6573	PORT MAP(
6574	data_in => crossbar_out_port14,
6575	reset => reset,
6576	clk => clk,
6577	wr_en =>crossbar_out_pulse14,
6578	data_out =>Port14_out,
6579	fifo_full =>fifo_out_full_signal(14),
6580	data_avalaible => data_available(14),
6581	rd_out_en => data_out_en(14)
6582	);
6583
6584	end generate port_out_switch14x14;
6585
6586
6587	-- switch 15 ports
6588	port_out_switch15x15 : if number_of_ports = 15 generate
6589
6590	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6591	PORT MAP(
6592	data_in => crossbar_out_port1,
6593	reset => reset,
6594	clk => clk,
6595	wr_en =>crossbar_out_pulse1,
6596	data_out =>Port1_out,
6597	fifo_full =>fifo_out_full_signal(1),
6598	data_avalaible => data_available(1),
6599	rd_out_en => data_out_en(1)
6600	);
6601
6602	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6603	PORT MAP(
6604	data_in => crossbar_out_port2,
6605	reset => reset,
6606	clk => clk,
6607	wr_en =>crossbar_out_pulse2,
6608	data_out =>Port2_out,
6609	fifo_full =>fifo_out_full_signal(2),
6610	data_avalaible => data_available(2),
6611	rd_out_en => data_out_en(2)
6612	);
6613
6614	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6615	PORT MAP(
6616	data_in => crossbar_out_port3,
6617	reset => reset,
6618	clk => clk,
6619	wr_en =>crossbar_out_pulse3,
6620	data_out =>Port3_out,
6621	fifo_full =>fifo_out_full_signal(3),
6622	data_avalaible => data_available(3),
6623	rd_out_en => data_out_en(3)
6624	);
6625
6626	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6627	PORT MAP(
6628	data_in => crossbar_out_port4,
6629	reset => reset,
6630	clk => clk,
6631	wr_en =>crossbar_out_pulse4,
6632	data_out =>Port4_out,
6633	fifo_full =>fifo_out_full_signal(4),
6634	data_avalaible => data_available(4),
6635	rd_out_en => data_out_en(4)
6636	);
6637
6638	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6639	PORT MAP(
6640	data_in => crossbar_out_port5,
6641	reset => reset,
6642	clk => clk,
6643	wr_en =>crossbar_out_pulse5,
6644	data_out =>Port5_out,
6645	fifo_full =>fifo_out_full_signal(5),
6646	data_avalaible => data_available(5),
6647	rd_out_en => data_out_en(5)
6648	);
6649
6650	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6651	PORT MAP(
6652	data_in => crossbar_out_port6,
6653	reset => reset,
6654	clk => clk,
6655	wr_en =>crossbar_out_pulse6,
6656	data_out =>Port6_out,
6657	fifo_full =>fifo_out_full_signal(6),
6658	data_avalaible => data_available(6),
6659	rd_out_en => data_out_en(6)
6660	);
6661
6662	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6663	PORT MAP(
6664	data_in => crossbar_out_port7,
6665	reset => reset,
6666	clk => clk,
6667	wr_en =>crossbar_out_pulse7,
6668	data_out =>Port7_out,
6669	fifo_full =>fifo_out_full_signal(7),
6670	data_avalaible => data_available(7),
6671	rd_out_en => data_out_en(7)
6672	);
6673
6674	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6675	PORT MAP(
6676	data_in => crossbar_out_port8,
6677	reset => reset,
6678	clk => clk,
6679	wr_en =>crossbar_out_pulse8,
6680	data_out =>Port8_out,
6681	fifo_full =>fifo_out_full_signal(8),
6682	data_avalaible => data_available(8),
6683	rd_out_en => data_out_en(8)
6684	);
6685
6686	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6687	PORT MAP(
6688	data_in => crossbar_out_port9,
6689	reset => reset,
6690	clk => clk,
6691	wr_en =>crossbar_out_pulse9,
6692	data_out =>Port9_out,
6693	fifo_full =>fifo_out_full_signal(9),
6694	data_avalaible => data_available(9),
6695	rd_out_en => data_out_en(9)
6696	);
6697
6698	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6699	PORT MAP(
6700	data_in => crossbar_out_port10,
6701	reset => reset,
6702	clk => clk,
6703	wr_en =>crossbar_out_pulse10,
6704	data_out =>Port10_out,
6705	fifo_full =>fifo_out_full_signal(10),
6706	data_avalaible => data_available(10),
6707	rd_out_en => data_out_en(10)
6708	);
6709
6710	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6711	PORT MAP(
6712	data_in => crossbar_out_port11,
6713	reset => reset,
6714	clk => clk,
6715	wr_en =>crossbar_out_pulse11,
6716	data_out =>Port11_out,
6717	fifo_full =>fifo_out_full_signal(11),
6718	data_avalaible => data_available(11),
6719	rd_out_en => data_out_en(11)
6720	);
6721
6722	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6723	PORT MAP(
6724	data_in => crossbar_out_port12,
6725	reset => reset,
6726	clk => clk,
6727	wr_en =>crossbar_out_pulse12,
6728	data_out =>Port12_out,
6729	fifo_full =>fifo_out_full_signal(12),
6730	data_avalaible => data_available(12),
6731	rd_out_en => data_out_en(12)
6732	);
6733
6734	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6735	PORT MAP(
6736	data_in => crossbar_out_port13,
6737	reset => reset,
6738	clk => clk,
6739	wr_en =>crossbar_out_pulse13,
6740	data_out =>Port13_out,
6741	fifo_full =>fifo_out_full_signal(13),
6742	data_avalaible => data_available(13),
6743	rd_out_en => data_out_en(13)
6744	);
6745
6746	PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6747	PORT MAP(
6748	data_in => crossbar_out_port14,
6749	reset => reset,
6750	clk => clk,
6751	wr_en =>crossbar_out_pulse14,
6752	data_out =>Port14_out,
6753	fifo_full =>fifo_out_full_signal(14),
6754	data_avalaible => data_available(14),
6755	rd_out_en => data_out_en(14)
6756	);
6757
6758	PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6759	PORT MAP(
6760	data_in => crossbar_out_port15,
6761	reset => reset,
6762	clk => clk,
6763	wr_en =>crossbar_out_pulse15,
6764	data_out =>Port15_out,
6765	fifo_full =>fifo_out_full_signal(15),
6766	data_avalaible => data_available(15),
6767	rd_out_en => data_out_en(15)
6768	);
6769
6770	end generate port_out_switch15x15;
6771
6772
6773	-- switch 16 ports
6774	port_out_switch16x16 : if number_of_ports = 16 generate
6775
6776	PORT1_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6777	PORT MAP(
6778	data_in => crossbar_out_port1,
6779	reset => reset,
6780	clk => clk,
6781	wr_en =>crossbar_out_pulse1,
6782	data_out =>Port1_out,
6783	fifo_full =>fifo_out_full_signal(1),
6784	data_avalaible => data_available(1),
6785	rd_out_en => data_out_en(1)
6786	);
6787
6788	PORT2_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6789	PORT MAP(
6790	data_in => crossbar_out_port2,
6791	reset => reset,
6792	clk => clk,
6793	wr_en =>crossbar_out_pulse2,
6794	data_out =>Port2_out,
6795	fifo_full =>fifo_out_full_signal(2),
6796	data_avalaible => data_available(2),
6797	rd_out_en => data_out_en(2)
6798	);
6799
6800	PORT3_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6801	PORT MAP(
6802	data_in => crossbar_out_port3,
6803	reset => reset,
6804	clk => clk,
6805	wr_en =>crossbar_out_pulse3,
6806	data_out =>Port3_out,
6807	fifo_full =>fifo_out_full_signal(3),
6808	data_avalaible => data_available(3),
6809	rd_out_en => data_out_en(3)
6810	);
6811
6812	PORT4_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6813	PORT MAP(
6814	data_in => crossbar_out_port4,
6815	reset => reset,
6816	clk => clk,
6817	wr_en =>crossbar_out_pulse4,
6818	data_out =>Port4_out,
6819	fifo_full =>fifo_out_full_signal(4),
6820	data_avalaible => data_available(4),
6821	rd_out_en => data_out_en(4)
6822	);
6823
6824	PORT5_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6825	PORT MAP(
6826	data_in => crossbar_out_port5,
6827	reset => reset,
6828	clk => clk,
6829	wr_en =>crossbar_out_pulse5,
6830	data_out =>Port5_out,
6831	fifo_full =>fifo_out_full_signal(5),
6832	data_avalaible => data_available(5),
6833	rd_out_en => data_out_en(5)
6834	);
6835
6836	PORT6_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6837	PORT MAP(
6838	data_in => crossbar_out_port6,
6839	reset => reset,
6840	clk => clk,
6841	wr_en =>crossbar_out_pulse6,
6842	data_out =>Port6_out,
6843	fifo_full =>fifo_out_full_signal(6),
6844	data_avalaible => data_available(6),
6845	rd_out_en => data_out_en(6)
6846	);
6847
6848	PORT7_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6849	PORT MAP(
6850	data_in => crossbar_out_port7,
6851	reset => reset,
6852	clk => clk,
6853	wr_en =>crossbar_out_pulse7,
6854	data_out =>Port7_out,
6855	fifo_full =>fifo_out_full_signal(7),
6856	data_avalaible => data_available(7),
6857	rd_out_en => data_out_en(7)
6858	);
6859
6860	PORT8_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6861	PORT MAP(
6862	data_in => crossbar_out_port8,
6863	reset => reset,
6864	clk => clk,
6865	wr_en =>crossbar_out_pulse8,
6866	data_out =>Port8_out,
6867	fifo_full =>fifo_out_full_signal(8),
6868	data_avalaible => data_available(8),
6869	rd_out_en => data_out_en(8)
6870	);
6871
6872	PORT9_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6873	PORT MAP(
6874	data_in => crossbar_out_port9,
6875	reset => reset,
6876	clk => clk,
6877	wr_en =>crossbar_out_pulse9,
6878	data_out =>Port9_out,
6879	fifo_full =>fifo_out_full_signal(9),
6880	data_avalaible => data_available(9),
6881	rd_out_en => data_out_en(9)
6882	);
6883
6884	PORT10_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6885	PORT MAP(
6886	data_in => crossbar_out_port10,
6887	reset => reset,
6888	clk => clk,
6889	wr_en =>crossbar_out_pulse10,
6890	data_out =>Port10_out,
6891	fifo_full =>fifo_out_full_signal(10),
6892	data_avalaible => data_available(10),
6893	rd_out_en => data_out_en(10)
6894	);
6895
6896	PORT11_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6897	PORT MAP(
6898	data_in => crossbar_out_port11,
6899	reset => reset,
6900	clk => clk,
6901	wr_en =>crossbar_out_pulse11,
6902	data_out =>Port11_out,
6903	fifo_full =>fifo_out_full_signal(11),
6904	data_avalaible => data_available(11),
6905	rd_out_en => data_out_en(11)
6906	);
6907
6908	PORT12_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6909	PORT MAP(
6910	data_in => crossbar_out_port12,
6911	reset => reset,
6912	clk => clk,
6913	wr_en =>crossbar_out_pulse12,
6914	data_out =>Port12_out,
6915	fifo_full =>fifo_out_full_signal(12),
6916	data_avalaible => data_available(12),
6917	rd_out_en => data_out_en(12)
6918	);
6919
6920	PORT13_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6921	PORT MAP(
6922	data_in => crossbar_out_port13,
6923	reset => reset,
6924	clk => clk,
6925	wr_en =>crossbar_out_pulse13,
6926	data_out =>Port13_out,
6927	fifo_full =>fifo_out_full_signal(13),
6928	data_avalaible => data_available(13),
6929	rd_out_en => data_out_en(13)
6930	);
6931
6932	PORT14_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6933	PORT MAP(
6934	data_in => crossbar_out_port14,
6935	reset => reset,
6936	clk => clk,
6937	wr_en =>crossbar_out_pulse14,
6938	data_out =>Port14_out,
6939	fifo_full =>fifo_out_full_signal(14),
6940	data_avalaible => data_available(14),
6941	rd_out_en => data_out_en(14)
6942	);
6943
6944	PORT15_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6945	PORT MAP(
6946	data_in => crossbar_out_port15,
6947	reset => reset,
6948	clk => clk,
6949	wr_en =>crossbar_out_pulse15,
6950	data_out =>Port15_out,
6951	fifo_full =>fifo_out_full_signal(15),
6952	data_avalaible => data_available(15),
6953	rd_out_en => data_out_en(15)
6954	);
6955
6956	PORT16_OUTPUT_PORT_MODULE: OUTPUT_PORT_MODULE
6957	PORT MAP(
6958	data_in => crossbar_out_port16,
6959	reset => reset,
6960	clk => clk,
6961	wr_en =>crossbar_out_pulse16,
6962	data_out =>Port16_out,
6963	fifo_full =>fifo_out_full_signal(16),
6964	data_avalaible => data_available(16),
6965	rd_out_en => data_out_en(16)
6966	);
6967
6968	end generate port_out_switch16x16;
6969
6970	-- intstanciation et connexion des crossbars du switch en fonction du nombre de ports
6971	-- le circuit genere depend du parametre generique nombre de ports
6972	-- switch 2 ports
6973	crossbar_switch2x2 : if number_of_ports = 2 generate
6974
6975	Switch_Crossbar2_2: Crossbar
6976	GENERIC MAP(number_of_crossbar_ports =>2)
6977	PORT MAP(
6978	Port1_in => crossbar_in_port1,
6979	Port2_in => crossbar_in_port2,
6980	Port3_in => "00000000",
6981	Port4_in => "00000000",
6982	Port5_in => "00000000",
6983	Port6_in => "00000000",
6984	Port7_in => "00000000",
6985	Port8_in => "00000000",
6986	Port9_in => "00000000",
6987	Port10_in => "00000000",
6988	Port11_in => "00000000",
6989	Port12_in => "00000000",
6990	Port13_in => "00000000",
6991	Port14_in => "00000000",
6992	Port15_in => "00000000",
6993	Port16_in => "00000000",
6994	Port1_pulse_in => crossbar_in_pulse1,
6995	Port2_pulse_in => crossbar_in_pulse2,
6996	Port3_pulse_in =>'0' ,
6997	Port4_pulse_in =>'0' ,
6998	Port5_pulse_in =>'0' ,
6999	Port6_pulse_in =>'0' ,
7000	Port7_pulse_in =>'0' ,
7001	Port8_pulse_in =>'0' ,
7002	Port9_pulse_in =>'0' ,
7003	Port10_pulse_in =>'0' ,
7004	Port11_pulse_in =>'0' ,
7005	Port12_pulse_in =>'0' ,
7006	Port13_pulse_in =>'0' ,
7007	Port14_pulse_in =>'0' ,
7008	Port15_pulse_in =>'0' ,
7009	Port16_pulse_in =>'0' ,
7010	Port1_pulse_out => crossbar_out_pulse1,
7011	Port2_pulse_out => crossbar_out_pulse2,
7012	Port1_out => crossbar_out_port1,
7013	Port2_out => crossbar_out_port2,
7014	Ctrl => Grant_signal);
7015	end generate crossbar_switch2x2;
7016
7017
7018	-- switch 3 ports
7019	crossbar_switch3x3 : if number_of_ports = 3 generate
7020
7021	Switch_Crossbar3_3: Crossbar
7022	GENERIC MAP(number_of_crossbar_ports =>3)
7023	PORT MAP(
7024	Port1_in => crossbar_in_port1,
7025	Port2_in => crossbar_in_port2,
7026	Port3_in => crossbar_in_port3,
7027	Port4_in => "00000000",
7028	Port5_in => "00000000",
7029	Port6_in => "00000000",
7030	Port7_in => "00000000",
7031	Port8_in => "00000000",
7032	Port9_in => "00000000",
7033	Port10_in => "00000000",
7034	Port11_in => "00000000",
7035	Port12_in => "00000000",
7036	Port13_in => "00000000",
7037	Port14_in => "00000000",
7038	Port15_in => "00000000",
7039	Port16_in => "00000000",
7040	Port1_pulse_in => crossbar_in_pulse1,
7041	Port2_pulse_in => crossbar_in_pulse2,
7042	Port3_pulse_in => crossbar_in_pulse3,
7043	Port4_pulse_in =>'0' ,
7044	Port5_pulse_in =>'0' ,
7045	Port6_pulse_in =>'0' ,
7046	Port7_pulse_in =>'0' ,
7047	Port8_pulse_in =>'0' ,
7048	Port9_pulse_in =>'0' ,
7049	Port10_pulse_in =>'0' ,
7050	Port11_pulse_in =>'0' ,
7051	Port12_pulse_in =>'0' ,
7052	Port13_pulse_in =>'0' ,
7053	Port14_pulse_in =>'0' ,
7054	Port15_pulse_in =>'0' ,
7055	Port16_pulse_in =>'0' ,
7056	Port1_pulse_out => crossbar_out_pulse1,
7057	Port2_pulse_out => crossbar_out_pulse2,
7058	Port3_pulse_out => crossbar_out_pulse3,
7059	Port1_out => crossbar_out_port1,
7060	Port2_out => crossbar_out_port2,
7061	Port3_out => crossbar_out_port3,
7062	Ctrl => Grant_signal);
7063	end generate crossbar_switch3x3;
7064
7065
7066	-- switch 4 ports
7067	crossbar_switch4x4 : if number_of_ports = 4 generate
7068
7069	Switch_Crossbar4_4: Crossbar
7070	GENERIC MAP(number_of_crossbar_ports =>4)
7071	PORT MAP(
7072	Port1_in => crossbar_in_port1,
7073	Port2_in => crossbar_in_port2,
7074	Port3_in => crossbar_in_port3,
7075	Port4_in => crossbar_in_port4,
7076	Port5_in => "00000000",
7077	Port6_in => "00000000",
7078	Port7_in => "00000000",
7079	Port8_in => "00000000",
7080	Port9_in => "00000000",
7081	Port10_in => "00000000",
7082	Port11_in => "00000000",
7083	Port12_in => "00000000",
7084	Port13_in => "00000000",
7085	Port14_in => "00000000",
7086	Port15_in => "00000000",
7087	Port16_in => "00000000",
7088	Port1_pulse_in => crossbar_in_pulse1,
7089	Port2_pulse_in => crossbar_in_pulse2,
7090	Port3_pulse_in => crossbar_in_pulse3,
7091	Port4_pulse_in => crossbar_in_pulse4,
7092	Port5_pulse_in =>'0' ,
7093	Port6_pulse_in =>'0' ,
7094	Port7_pulse_in =>'0' ,
7095	Port8_pulse_in =>'0' ,
7096	Port9_pulse_in =>'0' ,
7097	Port10_pulse_in =>'0' ,
7098	Port11_pulse_in =>'0' ,
7099	Port12_pulse_in =>'0' ,
7100	Port13_pulse_in =>'0' ,
7101	Port14_pulse_in =>'0' ,
7102	Port15_pulse_in =>'0' ,
7103	Port16_pulse_in =>'0' ,
7104	Port1_pulse_out => crossbar_out_pulse1,
7105	Port2_pulse_out => crossbar_out_pulse2,
7106	Port3_pulse_out => crossbar_out_pulse3,
7107	Port4_pulse_out => crossbar_out_pulse4,
7108	Port1_out => crossbar_out_port1,
7109	Port2_out => crossbar_out_port2,
7110	Port3_out => crossbar_out_port3,
7111	Port4_out => crossbar_out_port4,
7112	Ctrl => Grant_signal);
7113	end generate crossbar_switch4x4;
7114
7115
7116	-- switch 5 ports
7117	crossbar_switch5x5 : if number_of_ports = 5 generate
7118
7119	Switch_Crossbar5_5: Crossbar
7120	GENERIC MAP(number_of_crossbar_ports =>5)
7121	PORT MAP(
7122	Port1_in => crossbar_in_port1,
7123	Port2_in => crossbar_in_port2,
7124	Port3_in => crossbar_in_port3,
7125	Port4_in => crossbar_in_port4,
7126	Port5_in => crossbar_in_port5,
7127	Port6_in => "00000000",
7128	Port7_in => "00000000",
7129	Port8_in => "00000000",
7130	Port9_in => "00000000",
7131	Port10_in => "00000000",
7132	Port11_in => "00000000",
7133	Port12_in => "00000000",
7134	Port13_in => "00000000",
7135	Port14_in => "00000000",
7136	Port15_in => "00000000",
7137	Port16_in => "00000000",
7138	Port1_pulse_in => crossbar_in_pulse1,
7139	Port2_pulse_in => crossbar_in_pulse2,
7140	Port3_pulse_in => crossbar_in_pulse3,
7141	Port4_pulse_in => crossbar_in_pulse4,
7142	Port5_pulse_in => crossbar_in_pulse5,
7143	Port6_pulse_in =>'0' ,
7144	Port7_pulse_in =>'0' ,
7145	Port8_pulse_in =>'0' ,
7146	Port9_pulse_in =>'0' ,
7147	Port10_pulse_in =>'0' ,
7148	Port11_pulse_in =>'0' ,
7149	Port12_pulse_in =>'0' ,
7150	Port13_pulse_in =>'0' ,
7151	Port14_pulse_in =>'0' ,
7152	Port15_pulse_in =>'0' ,
7153	Port16_pulse_in =>'0' ,
7154	Port1_pulse_out => crossbar_out_pulse1,
7155	Port2_pulse_out => crossbar_out_pulse2,
7156	Port3_pulse_out => crossbar_out_pulse3,
7157	Port4_pulse_out => crossbar_out_pulse4,
7158	Port5_pulse_out => crossbar_out_pulse5,
7159	Port1_out => crossbar_out_port1,
7160	Port2_out => crossbar_out_port2,
7161	Port3_out => crossbar_out_port3,
7162	Port4_out => crossbar_out_port4,
7163	Port5_out => crossbar_out_port5,
7164	Ctrl => Grant_signal);
7165	end generate crossbar_switch5x5;
7166
7167
7168	-- switch 6 ports
7169	crossbar_switch6x6 : if number_of_ports = 6 generate
7170
7171	Switch_Crossbar6_6: Crossbar
7172	GENERIC MAP(number_of_crossbar_ports =>6)
7173	PORT MAP(
7174	Port1_in => crossbar_in_port1,
7175	Port2_in => crossbar_in_port2,
7176	Port3_in => crossbar_in_port3,
7177	Port4_in => crossbar_in_port4,
7178	Port5_in => crossbar_in_port5,
7179	Port6_in => crossbar_in_port6,
7180	Port7_in => "00000000",
7181	Port8_in => "00000000",
7182	Port9_in => "00000000",
7183	Port10_in => "00000000",
7184	Port11_in => "00000000",
7185	Port12_in => "00000000",
7186	Port13_in => "00000000",
7187	Port14_in => "00000000",
7188	Port15_in => "00000000",
7189	Port16_in => "00000000",
7190	Port1_pulse_in => crossbar_in_pulse1,
7191	Port2_pulse_in => crossbar_in_pulse2,
7192	Port3_pulse_in => crossbar_in_pulse3,
7193	Port4_pulse_in => crossbar_in_pulse4,
7194	Port5_pulse_in => crossbar_in_pulse5,
7195	Port6_pulse_in => crossbar_in_pulse6,
7196	Port7_pulse_in =>'0' ,
7197	Port8_pulse_in =>'0' ,
7198	Port9_pulse_in =>'0' ,
7199	Port10_pulse_in =>'0' ,
7200	Port11_pulse_in =>'0' ,
7201	Port12_pulse_in =>'0' ,
7202	Port13_pulse_in =>'0' ,
7203	Port14_pulse_in =>'0' ,
7204	Port15_pulse_in =>'0' ,
7205	Port16_pulse_in =>'0' ,
7206	Port1_pulse_out => crossbar_out_pulse1,
7207	Port2_pulse_out => crossbar_out_pulse2,
7208	Port3_pulse_out => crossbar_out_pulse3,
7209	Port4_pulse_out => crossbar_out_pulse4,
7210	Port5_pulse_out => crossbar_out_pulse5,
7211	Port6_pulse_out => crossbar_out_pulse6,
7212	Port1_out => crossbar_out_port1,
7213	Port2_out => crossbar_out_port2,
7214	Port3_out => crossbar_out_port3,
7215	Port4_out => crossbar_out_port4,
7216	Port5_out => crossbar_out_port5,
7217	Port6_out => crossbar_out_port6,
7218	Ctrl => Grant_signal);
7219	end generate crossbar_switch6x6;
7220
7221
7222	-- switch 7 ports
7223	crossbar_switch7x7 : if number_of_ports = 7 generate
7224
7225	Switch_Crossbar7_7: Crossbar
7226	GENERIC MAP(number_of_crossbar_ports =>7)
7227	PORT MAP(
7228	Port1_in => crossbar_in_port1,
7229	Port2_in => crossbar_in_port2,
7230	Port3_in => crossbar_in_port3,
7231	Port4_in => crossbar_in_port4,
7232	Port5_in => crossbar_in_port5,
7233	Port6_in => crossbar_in_port6,
7234	Port7_in => crossbar_in_port7,
7235	Port8_in => "00000000",
7236	Port9_in => "00000000",
7237	Port10_in => "00000000",
7238	Port11_in => "00000000",
7239	Port12_in => "00000000",
7240	Port13_in => "00000000",
7241	Port14_in => "00000000",
7242	Port15_in => "00000000",
7243	Port16_in => "00000000",
7244	Port1_pulse_in => crossbar_in_pulse1,
7245	Port2_pulse_in => crossbar_in_pulse2,
7246	Port3_pulse_in => crossbar_in_pulse3,
7247	Port4_pulse_in => crossbar_in_pulse4,
7248	Port5_pulse_in => crossbar_in_pulse5,
7249	Port6_pulse_in => crossbar_in_pulse6,
7250	Port7_pulse_in => crossbar_in_pulse7,
7251	Port8_pulse_in =>'0' ,
7252	Port9_pulse_in =>'0' ,
7253	Port10_pulse_in =>'0' ,
7254	Port11_pulse_in =>'0' ,
7255	Port12_pulse_in =>'0' ,
7256	Port13_pulse_in =>'0' ,
7257	Port14_pulse_in =>'0' ,
7258	Port15_pulse_in =>'0' ,
7259	Port16_pulse_in =>'0' ,
7260	Port1_pulse_out => crossbar_out_pulse1,
7261	Port2_pulse_out => crossbar_out_pulse2,
7262	Port3_pulse_out => crossbar_out_pulse3,
7263	Port4_pulse_out => crossbar_out_pulse4,
7264	Port5_pulse_out => crossbar_out_pulse5,
7265	Port6_pulse_out => crossbar_out_pulse6,
7266	Port7_pulse_out => crossbar_out_pulse7,
7267	Port1_out => crossbar_out_port1,
7268	Port2_out => crossbar_out_port2,
7269	Port3_out => crossbar_out_port3,
7270	Port4_out => crossbar_out_port4,
7271	Port5_out => crossbar_out_port5,
7272	Port6_out => crossbar_out_port6,
7273	Port7_out => crossbar_out_port7,
7274	Ctrl => Grant_signal);
7275	end generate crossbar_switch7x7;
7276
7277
7278	-- switch 8 ports
7279	crossbar_switch8x8 : if number_of_ports = 8 generate
7280
7281	Switch_Crossbar8_8: Crossbar
7282	GENERIC MAP(number_of_crossbar_ports =>8)
7283	PORT MAP(
7284	Port1_in => crossbar_in_port1,
7285	Port2_in => crossbar_in_port2,
7286	Port3_in => crossbar_in_port3,
7287	Port4_in => crossbar_in_port4,
7288	Port5_in => crossbar_in_port5,
7289	Port6_in => crossbar_in_port6,
7290	Port7_in => crossbar_in_port7,
7291	Port8_in => crossbar_in_port8,
7292	Port9_in => "00000000",
7293	Port10_in => "00000000",
7294	Port11_in => "00000000",
7295	Port12_in => "00000000",
7296	Port13_in => "00000000",
7297	Port14_in => "00000000",
7298	Port15_in => "00000000",
7299	Port16_in => "00000000",
7300	Port1_pulse_in => crossbar_in_pulse1,
7301	Port2_pulse_in => crossbar_in_pulse2,
7302	Port3_pulse_in => crossbar_in_pulse3,
7303	Port4_pulse_in => crossbar_in_pulse4,
7304	Port5_pulse_in => crossbar_in_pulse5,
7305	Port6_pulse_in => crossbar_in_pulse6,
7306	Port7_pulse_in => crossbar_in_pulse7,
7307	Port8_pulse_in => crossbar_in_pulse8,
7308	Port9_pulse_in =>'0' ,
7309	Port10_pulse_in =>'0' ,
7310	Port11_pulse_in =>'0' ,
7311	Port12_pulse_in =>'0' ,
7312	Port13_pulse_in =>'0' ,
7313	Port14_pulse_in =>'0' ,
7314	Port15_pulse_in =>'0' ,
7315	Port16_pulse_in =>'0' ,
7316	Port1_pulse_out => crossbar_out_pulse1,
7317	Port2_pulse_out => crossbar_out_pulse2,
7318	Port3_pulse_out => crossbar_out_pulse3,
7319	Port4_pulse_out => crossbar_out_pulse4,
7320	Port5_pulse_out => crossbar_out_pulse5,
7321	Port6_pulse_out => crossbar_out_pulse6,
7322	Port7_pulse_out => crossbar_out_pulse7,
7323	Port8_pulse_out => crossbar_out_pulse8,
7324	Port1_out => crossbar_out_port1,
7325	Port2_out => crossbar_out_port2,
7326	Port3_out => crossbar_out_port3,
7327	Port4_out => crossbar_out_port4,
7328	Port5_out => crossbar_out_port5,
7329	Port6_out => crossbar_out_port6,
7330	Port7_out => crossbar_out_port7,
7331	Port8_out => crossbar_out_port8,
7332	Ctrl => Grant_signal);
7333	end generate crossbar_switch8x8;
7334
7335
7336	-- switch 9 ports
7337	crossbar_switch9x9 : if number_of_ports = 9 generate
7338
7339	Switch_Crossbar9_9: Crossbar
7340	GENERIC MAP(number_of_crossbar_ports =>9)
7341	PORT MAP(
7342	Port1_in => crossbar_in_port1,
7343	Port2_in => crossbar_in_port2,
7344	Port3_in => crossbar_in_port3,
7345	Port4_in => crossbar_in_port4,
7346	Port5_in => crossbar_in_port5,
7347	Port6_in => crossbar_in_port6,
7348	Port7_in => crossbar_in_port7,
7349	Port8_in => crossbar_in_port8,
7350	Port9_in => crossbar_in_port9,
7351	Port10_in => "00000000",
7352	Port11_in => "00000000",
7353	Port12_in => "00000000",
7354	Port13_in => "00000000",
7355	Port14_in => "00000000",
7356	Port15_in => "00000000",
7357	Port16_in => "00000000",
7358	Port1_pulse_in => crossbar_in_pulse1,
7359	Port2_pulse_in => crossbar_in_pulse2,
7360	Port3_pulse_in => crossbar_in_pulse3,
7361	Port4_pulse_in => crossbar_in_pulse4,
7362	Port5_pulse_in => crossbar_in_pulse5,
7363	Port6_pulse_in => crossbar_in_pulse6,
7364	Port7_pulse_in => crossbar_in_pulse7,
7365	Port8_pulse_in => crossbar_in_pulse8,
7366	Port9_pulse_in => crossbar_in_pulse9,
7367	Port10_pulse_in =>'0' ,
7368	Port11_pulse_in =>'0' ,
7369	Port12_pulse_in =>'0' ,
7370	Port13_pulse_in =>'0' ,
7371	Port14_pulse_in =>'0' ,
7372	Port15_pulse_in =>'0' ,
7373	Port16_pulse_in =>'0' ,
7374	Port1_pulse_out => crossbar_out_pulse1,
7375	Port2_pulse_out => crossbar_out_pulse2,
7376	Port3_pulse_out => crossbar_out_pulse3,
7377	Port4_pulse_out => crossbar_out_pulse4,
7378	Port5_pulse_out => crossbar_out_pulse5,
7379	Port6_pulse_out => crossbar_out_pulse6,
7380	Port7_pulse_out => crossbar_out_pulse7,
7381	Port8_pulse_out => crossbar_out_pulse8,
7382	Port9_pulse_out => crossbar_out_pulse9,
7383	Port1_out => crossbar_out_port1,
7384	Port2_out => crossbar_out_port2,
7385	Port3_out => crossbar_out_port3,
7386	Port4_out => crossbar_out_port4,
7387	Port5_out => crossbar_out_port5,
7388	Port6_out => crossbar_out_port6,
7389	Port7_out => crossbar_out_port7,
7390	Port8_out => crossbar_out_port8,
7391	Port9_out => crossbar_out_port9,
7392	Ctrl => Grant_signal);
7393	end generate crossbar_switch9x9;
7394
7395
7396	-- switch 10 ports
7397	crossbar_switch10x10 : if number_of_ports = 10 generate
7398
7399	Switch_Crossbar10_10: Crossbar
7400	GENERIC MAP(number_of_crossbar_ports =>10)
7401	PORT MAP(
7402	Port1_in => crossbar_in_port1,
7403	Port2_in => crossbar_in_port2,
7404	Port3_in => crossbar_in_port3,
7405	Port4_in => crossbar_in_port4,
7406	Port5_in => crossbar_in_port5,
7407	Port6_in => crossbar_in_port6,
7408	Port7_in => crossbar_in_port7,
7409	Port8_in => crossbar_in_port8,
7410	Port9_in => crossbar_in_port9,
7411	Port10_in => crossbar_in_port10,
7412	Port11_in => "00000000",
7413	Port12_in => "00000000",
7414	Port13_in => "00000000",
7415	Port14_in => "00000000",
7416	Port15_in => "00000000",
7417	Port16_in => "00000000",
7418	Port1_pulse_in => crossbar_in_pulse1,
7419	Port2_pulse_in => crossbar_in_pulse2,
7420	Port3_pulse_in => crossbar_in_pulse3,
7421	Port4_pulse_in => crossbar_in_pulse4,
7422	Port5_pulse_in => crossbar_in_pulse5,
7423	Port6_pulse_in => crossbar_in_pulse6,
7424	Port7_pulse_in => crossbar_in_pulse7,
7425	Port8_pulse_in => crossbar_in_pulse8,
7426	Port9_pulse_in => crossbar_in_pulse9,
7427	Port10_pulse_in => crossbar_in_pulse10,
7428	Port11_pulse_in =>'0' ,
7429	Port12_pulse_in =>'0' ,
7430	Port13_pulse_in =>'0' ,
7431	Port14_pulse_in =>'0' ,
7432	Port15_pulse_in =>'0' ,
7433	Port16_pulse_in =>'0' ,
7434	Port1_pulse_out => crossbar_out_pulse1,
7435	Port2_pulse_out => crossbar_out_pulse2,
7436	Port3_pulse_out => crossbar_out_pulse3,
7437	Port4_pulse_out => crossbar_out_pulse4,
7438	Port5_pulse_out => crossbar_out_pulse5,
7439	Port6_pulse_out => crossbar_out_pulse6,
7440	Port7_pulse_out => crossbar_out_pulse7,
7441	Port8_pulse_out => crossbar_out_pulse8,
7442	Port9_pulse_out => crossbar_out_pulse9,
7443	Port10_pulse_out => crossbar_out_pulse10,
7444	Port1_out => crossbar_out_port1,
7445	Port2_out => crossbar_out_port2,
7446	Port3_out => crossbar_out_port3,
7447	Port4_out => crossbar_out_port4,
7448	Port5_out => crossbar_out_port5,
7449	Port6_out => crossbar_out_port6,
7450	Port7_out => crossbar_out_port7,
7451	Port8_out => crossbar_out_port8,
7452	Port9_out => crossbar_out_port9,
7453	Port10_out => crossbar_out_port10,
7454	Ctrl => Grant_signal);
7455	end generate crossbar_switch10x10;
7456
7457
7458	-- switch 11 ports
7459	crossbar_switch11x11 : if number_of_ports = 11 generate
7460
7461	Switch_Crossbar11_11: Crossbar
7462	GENERIC MAP(number_of_crossbar_ports =>11)
7463	PORT MAP(
7464	Port1_in => crossbar_in_port1,
7465	Port2_in => crossbar_in_port2,
7466	Port3_in => crossbar_in_port3,
7467	Port4_in => crossbar_in_port4,
7468	Port5_in => crossbar_in_port5,
7469	Port6_in => crossbar_in_port6,
7470	Port7_in => crossbar_in_port7,
7471	Port8_in => crossbar_in_port8,
7472	Port9_in => crossbar_in_port9,
7473	Port10_in => crossbar_in_port10,
7474	Port11_in => crossbar_in_port11,
7475	Port12_in => "00000000",
7476	Port13_in => "00000000",
7477	Port14_in => "00000000",
7478	Port15_in => "00000000",
7479	Port16_in => "00000000",
7480	Port1_pulse_in => crossbar_in_pulse1,
7481	Port2_pulse_in => crossbar_in_pulse2,
7482	Port3_pulse_in => crossbar_in_pulse3,
7483	Port4_pulse_in => crossbar_in_pulse4,
7484	Port5_pulse_in => crossbar_in_pulse5,
7485	Port6_pulse_in => crossbar_in_pulse6,
7486	Port7_pulse_in => crossbar_in_pulse7,
7487	Port8_pulse_in => crossbar_in_pulse8,
7488	Port9_pulse_in => crossbar_in_pulse9,
7489	Port10_pulse_in => crossbar_in_pulse10,
7490	Port11_pulse_in => crossbar_in_pulse11,
7491	Port12_pulse_in =>'0' ,
7492	Port13_pulse_in =>'0' ,
7493	Port14_pulse_in =>'0' ,
7494	Port15_pulse_in =>'0' ,
7495	Port16_pulse_in =>'0' ,
7496	Port1_pulse_out => crossbar_out_pulse1,
7497	Port2_pulse_out => crossbar_out_pulse2,
7498	Port3_pulse_out => crossbar_out_pulse3,
7499	Port4_pulse_out => crossbar_out_pulse4,
7500	Port5_pulse_out => crossbar_out_pulse5,
7501	Port6_pulse_out => crossbar_out_pulse6,
7502	Port7_pulse_out => crossbar_out_pulse7,
7503	Port8_pulse_out => crossbar_out_pulse8,
7504	Port9_pulse_out => crossbar_out_pulse9,
7505	Port10_pulse_out => crossbar_out_pulse10,
7506	Port11_pulse_out => crossbar_out_pulse11,
7507	Port1_out => crossbar_out_port1,
7508	Port2_out => crossbar_out_port2,
7509	Port3_out => crossbar_out_port3,
7510	Port4_out => crossbar_out_port4,
7511	Port5_out => crossbar_out_port5,
7512	Port6_out => crossbar_out_port6,
7513	Port7_out => crossbar_out_port7,
7514	Port8_out => crossbar_out_port8,
7515	Port9_out => crossbar_out_port9,
7516	Port10_out => crossbar_out_port10,
7517	Port11_out => crossbar_out_port11,
7518	Ctrl => Grant_signal);
7519	end generate crossbar_switch11x11;
7520
7521
7522	-- switch 12 ports
7523	crossbar_switch12x12 : if number_of_ports = 12 generate
7524
7525	Switch_Crossbar12_12: Crossbar
7526	GENERIC MAP(number_of_crossbar_ports =>12)
7527	PORT MAP(
7528	Port1_in => crossbar_in_port1,
7529	Port2_in => crossbar_in_port2,
7530	Port3_in => crossbar_in_port3,
7531	Port4_in => crossbar_in_port4,
7532	Port5_in => crossbar_in_port5,
7533	Port6_in => crossbar_in_port6,
7534	Port7_in => crossbar_in_port7,
7535	Port8_in => crossbar_in_port8,
7536	Port9_in => crossbar_in_port9,
7537	Port10_in => crossbar_in_port10,
7538	Port11_in => crossbar_in_port11,
7539	Port12_in => crossbar_in_port12,
7540	Port13_in => "00000000",
7541	Port14_in => "00000000",
7542	Port15_in => "00000000",
7543	Port16_in => "00000000",
7544	Port1_pulse_in => crossbar_in_pulse1,
7545	Port2_pulse_in => crossbar_in_pulse2,
7546	Port3_pulse_in => crossbar_in_pulse3,
7547	Port4_pulse_in => crossbar_in_pulse4,
7548	Port5_pulse_in => crossbar_in_pulse5,
7549	Port6_pulse_in => crossbar_in_pulse6,
7550	Port7_pulse_in => crossbar_in_pulse7,
7551	Port8_pulse_in => crossbar_in_pulse8,
7552	Port9_pulse_in => crossbar_in_pulse9,
7553	Port10_pulse_in => crossbar_in_pulse10,
7554	Port11_pulse_in => crossbar_in_pulse11,
7555	Port12_pulse_in => crossbar_in_pulse12,
7556	Port13_pulse_in =>'0' ,
7557	Port14_pulse_in =>'0' ,
7558	Port15_pulse_in =>'0' ,
7559	Port16_pulse_in =>'0' ,
7560	Port1_pulse_out => crossbar_out_pulse1,
7561	Port2_pulse_out => crossbar_out_pulse2,
7562	Port3_pulse_out => crossbar_out_pulse3,
7563	Port4_pulse_out => crossbar_out_pulse4,
7564	Port5_pulse_out => crossbar_out_pulse5,
7565	Port6_pulse_out => crossbar_out_pulse6,
7566	Port7_pulse_out => crossbar_out_pulse7,
7567	Port8_pulse_out => crossbar_out_pulse8,
7568	Port9_pulse_out => crossbar_out_pulse9,
7569	Port10_pulse_out => crossbar_out_pulse10,
7570	Port11_pulse_out => crossbar_out_pulse11,
7571	Port12_pulse_out => crossbar_out_pulse12,
7572	Port1_out => crossbar_out_port1,
7573	Port2_out => crossbar_out_port2,
7574	Port3_out => crossbar_out_port3,
7575	Port4_out => crossbar_out_port4,
7576	Port5_out => crossbar_out_port5,
7577	Port6_out => crossbar_out_port6,
7578	Port7_out => crossbar_out_port7,
7579	Port8_out => crossbar_out_port8,
7580	Port9_out => crossbar_out_port9,
7581	Port10_out => crossbar_out_port10,
7582	Port11_out => crossbar_out_port11,
7583	Port12_out => crossbar_out_port12,
7584	Ctrl => Grant_signal);
7585	end generate crossbar_switch12x12;
7586
7587
7588	-- switch 13 ports
7589	crossbar_switch13x13 : if number_of_ports = 13 generate
7590
7591	Switch_Crossbar13_13: Crossbar
7592	GENERIC MAP(number_of_crossbar_ports =>13)
7593	PORT MAP(
7594	Port1_in => crossbar_in_port1,
7595	Port2_in => crossbar_in_port2,
7596	Port3_in => crossbar_in_port3,
7597	Port4_in => crossbar_in_port4,
7598	Port5_in => crossbar_in_port5,
7599	Port6_in => crossbar_in_port6,
7600	Port7_in => crossbar_in_port7,
7601	Port8_in => crossbar_in_port8,
7602	Port9_in => crossbar_in_port9,
7603	Port10_in => crossbar_in_port10,
7604	Port11_in => crossbar_in_port11,
7605	Port12_in => crossbar_in_port12,
7606	Port13_in => crossbar_in_port13,
7607	Port14_in => "00000000",
7608	Port15_in => "00000000",
7609	Port16_in => "00000000",
7610	Port1_pulse_in => crossbar_in_pulse1,
7611	Port2_pulse_in => crossbar_in_pulse2,
7612	Port3_pulse_in => crossbar_in_pulse3,
7613	Port4_pulse_in => crossbar_in_pulse4,
7614	Port5_pulse_in => crossbar_in_pulse5,
7615	Port6_pulse_in => crossbar_in_pulse6,
7616	Port7_pulse_in => crossbar_in_pulse7,
7617	Port8_pulse_in => crossbar_in_pulse8,
7618	Port9_pulse_in => crossbar_in_pulse9,
7619	Port10_pulse_in => crossbar_in_pulse10,
7620	Port11_pulse_in => crossbar_in_pulse11,
7621	Port12_pulse_in => crossbar_in_pulse12,
7622	Port13_pulse_in => crossbar_in_pulse13,
7623	Port14_pulse_in =>'0' ,
7624	Port15_pulse_in =>'0' ,
7625	Port16_pulse_in =>'0' ,
7626	Port1_pulse_out => crossbar_out_pulse1,
7627	Port2_pulse_out => crossbar_out_pulse2,
7628	Port3_pulse_out => crossbar_out_pulse3,
7629	Port4_pulse_out => crossbar_out_pulse4,
7630	Port5_pulse_out => crossbar_out_pulse5,
7631	Port6_pulse_out => crossbar_out_pulse6,
7632	Port7_pulse_out => crossbar_out_pulse7,
7633	Port8_pulse_out => crossbar_out_pulse8,
7634	Port9_pulse_out => crossbar_out_pulse9,
7635	Port10_pulse_out => crossbar_out_pulse10,
7636	Port11_pulse_out => crossbar_out_pulse11,
7637	Port12_pulse_out => crossbar_out_pulse12,
7638	Port13_pulse_out => crossbar_out_pulse13,
7639	Port1_out => crossbar_out_port1,
7640	Port2_out => crossbar_out_port2,
7641	Port3_out => crossbar_out_port3,
7642	Port4_out => crossbar_out_port4,
7643	Port5_out => crossbar_out_port5,
7644	Port6_out => crossbar_out_port6,
7645	Port7_out => crossbar_out_port7,
7646	Port8_out => crossbar_out_port8,
7647	Port9_out => crossbar_out_port9,
7648	Port10_out => crossbar_out_port10,
7649	Port11_out => crossbar_out_port11,
7650	Port12_out => crossbar_out_port12,
7651	Port13_out => crossbar_out_port13,
7652	Ctrl => Grant_signal);
7653	end generate crossbar_switch13x13;
7654
7655
7656	-- switch 14 ports
7657	crossbar_switch14x14 : if number_of_ports = 14 generate
7658
7659	Switch_Crossbar14_14: Crossbar
7660	GENERIC MAP(number_of_crossbar_ports =>14)
7661	PORT MAP(
7662	Port1_in => crossbar_in_port1,
7663	Port2_in => crossbar_in_port2,
7664	Port3_in => crossbar_in_port3,
7665	Port4_in => crossbar_in_port4,
7666	Port5_in => crossbar_in_port5,
7667	Port6_in => crossbar_in_port6,
7668	Port7_in => crossbar_in_port7,
7669	Port8_in => crossbar_in_port8,
7670	Port9_in => crossbar_in_port9,
7671	Port10_in => crossbar_in_port10,
7672	Port11_in => crossbar_in_port11,
7673	Port12_in => crossbar_in_port12,
7674	Port13_in => crossbar_in_port13,
7675	Port14_in => crossbar_in_port14,
7676	Port15_in => "00000000",
7677	Port16_in => "00000000",
7678	Port1_pulse_in => crossbar_in_pulse1,
7679	Port2_pulse_in => crossbar_in_pulse2,
7680	Port3_pulse_in => crossbar_in_pulse3,
7681	Port4_pulse_in => crossbar_in_pulse4,
7682	Port5_pulse_in => crossbar_in_pulse5,
7683	Port6_pulse_in => crossbar_in_pulse6,
7684	Port7_pulse_in => crossbar_in_pulse7,
7685	Port8_pulse_in => crossbar_in_pulse8,
7686	Port9_pulse_in => crossbar_in_pulse9,
7687	Port10_pulse_in => crossbar_in_pulse10,
7688	Port11_pulse_in => crossbar_in_pulse11,
7689	Port12_pulse_in => crossbar_in_pulse12,
7690	Port13_pulse_in => crossbar_in_pulse13,
7691	Port14_pulse_in => crossbar_in_pulse14,
7692	Port15_pulse_in =>'0' ,
7693	Port16_pulse_in =>'0' ,
7694	Port1_pulse_out => crossbar_out_pulse1,
7695	Port2_pulse_out => crossbar_out_pulse2,
7696	Port3_pulse_out => crossbar_out_pulse3,
7697	Port4_pulse_out => crossbar_out_pulse4,
7698	Port5_pulse_out => crossbar_out_pulse5,
7699	Port6_pulse_out => crossbar_out_pulse6,
7700	Port7_pulse_out => crossbar_out_pulse7,
7701	Port8_pulse_out => crossbar_out_pulse8,
7702	Port9_pulse_out => crossbar_out_pulse9,
7703	Port10_pulse_out => crossbar_out_pulse10,
7704	Port11_pulse_out => crossbar_out_pulse11,
7705	Port12_pulse_out => crossbar_out_pulse12,
7706	Port13_pulse_out => crossbar_out_pulse13,
7707	Port14_pulse_out => crossbar_out_pulse14,
7708	Port1_out => crossbar_out_port1,
7709	Port2_out => crossbar_out_port2,
7710	Port3_out => crossbar_out_port3,
7711	Port4_out => crossbar_out_port4,
7712	Port5_out => crossbar_out_port5,
7713	Port6_out => crossbar_out_port6,
7714	Port7_out => crossbar_out_port7,
7715	Port8_out => crossbar_out_port8,
7716	Port9_out => crossbar_out_port9,
7717	Port10_out => crossbar_out_port10,
7718	Port11_out => crossbar_out_port11,
7719	Port12_out => crossbar_out_port12,
7720	Port13_out => crossbar_out_port13,
7721	Port14_out => crossbar_out_port14,
7722	Ctrl => Grant_signal);
7723	end generate crossbar_switch14x14;
7724
7725
7726	-- switch 15 ports
7727	crossbar_switch15x15 : if number_of_ports = 15 generate
7728
7729	Switch_Crossbar15_15: Crossbar
7730	GENERIC MAP(number_of_crossbar_ports =>15)
7731	PORT MAP(
7732	Port1_in => crossbar_in_port1,
7733	Port2_in => crossbar_in_port2,
7734	Port3_in => crossbar_in_port3,
7735	Port4_in => crossbar_in_port4,
7736	Port5_in => crossbar_in_port5,
7737	Port6_in => crossbar_in_port6,
7738	Port7_in => crossbar_in_port7,
7739	Port8_in => crossbar_in_port8,
7740	Port9_in => crossbar_in_port9,
7741	Port10_in => crossbar_in_port10,
7742	Port11_in => crossbar_in_port11,
7743	Port12_in => crossbar_in_port12,
7744	Port13_in => crossbar_in_port13,
7745	Port14_in => crossbar_in_port14,
7746	Port15_in => crossbar_in_port15,
7747	Port16_in => "00000000",
7748	Port1_pulse_in => crossbar_in_pulse1,
7749	Port2_pulse_in => crossbar_in_pulse2,
7750	Port3_pulse_in => crossbar_in_pulse3,
7751	Port4_pulse_in => crossbar_in_pulse4,
7752	Port5_pulse_in => crossbar_in_pulse5,
7753	Port6_pulse_in => crossbar_in_pulse6,
7754	Port7_pulse_in => crossbar_in_pulse7,
7755	Port8_pulse_in => crossbar_in_pulse8,
7756	Port9_pulse_in => crossbar_in_pulse9,
7757	Port10_pulse_in => crossbar_in_pulse10,
7758	Port11_pulse_in => crossbar_in_pulse11,
7759	Port12_pulse_in => crossbar_in_pulse12,
7760	Port13_pulse_in => crossbar_in_pulse13,
7761	Port14_pulse_in => crossbar_in_pulse14,
7762	Port15_pulse_in => crossbar_in_pulse15,
7763	Port16_pulse_in =>'0' ,
7764	Port1_pulse_out => crossbar_out_pulse1,
7765	Port2_pulse_out => crossbar_out_pulse2,
7766	Port3_pulse_out => crossbar_out_pulse3,
7767	Port4_pulse_out => crossbar_out_pulse4,
7768	Port5_pulse_out => crossbar_out_pulse5,
7769	Port6_pulse_out => crossbar_out_pulse6,
7770	Port7_pulse_out => crossbar_out_pulse7,
7771	Port8_pulse_out => crossbar_out_pulse8,
7772	Port9_pulse_out => crossbar_out_pulse9,
7773	Port10_pulse_out => crossbar_out_pulse10,
7774	Port11_pulse_out => crossbar_out_pulse11,
7775	Port12_pulse_out => crossbar_out_pulse12,
7776	Port13_pulse_out => crossbar_out_pulse13,
7777	Port14_pulse_out => crossbar_out_pulse14,
7778	Port15_pulse_out => crossbar_out_pulse15,
7779	Port1_out => crossbar_out_port1,
7780	Port2_out => crossbar_out_port2,
7781	Port3_out => crossbar_out_port3,
7782	Port4_out => crossbar_out_port4,
7783	Port5_out => crossbar_out_port5,
7784	Port6_out => crossbar_out_port6,
7785	Port7_out => crossbar_out_port7,
7786	Port8_out => crossbar_out_port8,
7787	Port9_out => crossbar_out_port9,
7788	Port10_out => crossbar_out_port10,
7789	Port11_out => crossbar_out_port11,
7790	Port12_out => crossbar_out_port12,
7791	Port13_out => crossbar_out_port13,
7792	Port14_out => crossbar_out_port14,
7793	Port15_out => crossbar_out_port15,
7794	Ctrl => Grant_signal);
7795	end generate crossbar_switch15x15;
7796
7797
7798	-- switch 16 ports
7799	crossbar_switch16x16 : if number_of_ports = 16 generate
7800
7801	Switch_Crossbar16_16: Crossbar
7802	GENERIC MAP(number_of_crossbar_ports =>16)
7803	PORT MAP(
7804	Port1_in => crossbar_in_port1,
7805	Port2_in => crossbar_in_port2,
7806	Port3_in => crossbar_in_port3,
7807	Port4_in => crossbar_in_port4,
7808	Port5_in => crossbar_in_port5,
7809	Port6_in => crossbar_in_port6,
7810	Port7_in => crossbar_in_port7,
7811	Port8_in => crossbar_in_port8,
7812	Port9_in => crossbar_in_port9,
7813	Port10_in => crossbar_in_port10,
7814	Port11_in => crossbar_in_port11,
7815	Port12_in => crossbar_in_port12,
7816	Port13_in => crossbar_in_port13,
7817	Port14_in => crossbar_in_port14,
7818	Port15_in => crossbar_in_port15,
7819	Port16_in => crossbar_in_port16,
7820	Port1_pulse_in => crossbar_in_pulse1,
7821	Port2_pulse_in => crossbar_in_pulse2,
7822	Port3_pulse_in => crossbar_in_pulse3,
7823	Port4_pulse_in => crossbar_in_pulse4,
7824	Port5_pulse_in => crossbar_in_pulse5,
7825	Port6_pulse_in => crossbar_in_pulse6,
7826	Port7_pulse_in => crossbar_in_pulse7,
7827	Port8_pulse_in => crossbar_in_pulse8,
7828	Port9_pulse_in => crossbar_in_pulse9,
7829	Port10_pulse_in => crossbar_in_pulse10,
7830	Port11_pulse_in => crossbar_in_pulse11,
7831	Port12_pulse_in => crossbar_in_pulse12,
7832	Port13_pulse_in => crossbar_in_pulse13,
7833	Port14_pulse_in => crossbar_in_pulse14,
7834	Port15_pulse_in => crossbar_in_pulse15,
7835	Port16_pulse_in => crossbar_in_pulse16,
7836	Port1_pulse_out => crossbar_out_pulse1,
7837	Port2_pulse_out => crossbar_out_pulse2,
7838	Port3_pulse_out => crossbar_out_pulse3,
7839	Port4_pulse_out => crossbar_out_pulse4,
7840	Port5_pulse_out => crossbar_out_pulse5,
7841	Port6_pulse_out => crossbar_out_pulse6,
7842	Port7_pulse_out => crossbar_out_pulse7,
7843	Port8_pulse_out => crossbar_out_pulse8,
7844	Port9_pulse_out => crossbar_out_pulse9,
7845	Port10_pulse_out => crossbar_out_pulse10,
7846	Port11_pulse_out => crossbar_out_pulse11,
7847	Port12_pulse_out => crossbar_out_pulse12,
7848	Port13_pulse_out => crossbar_out_pulse13,
7849	Port14_pulse_out => crossbar_out_pulse14,
7850	Port15_pulse_out => crossbar_out_pulse15,
7851	Port16_pulse_out => crossbar_out_pulse16,
7852	Port1_out => crossbar_out_port1,
7853	Port2_out => crossbar_out_port2,
7854	Port3_out => crossbar_out_port3,
7855	Port4_out => crossbar_out_port4,
7856	Port5_out => crossbar_out_port5,
7857	Port6_out => crossbar_out_port6,
7858	Port7_out => crossbar_out_port7,
7859	Port8_out => crossbar_out_port8,
7860	Port9_out => crossbar_out_port9,
7861	Port10_out => crossbar_out_port10,
7862	Port11_out => crossbar_out_port11,
7863	Port12_out => crossbar_out_port12,
7864	Port13_out => crossbar_out_port13,
7865	Port14_out => crossbar_out_port14,
7866	Port15_out => crossbar_out_port15,
7867	Port16_out => crossbar_out_port16,
7868	Ctrl => Grant_signal);
7869	end generate crossbar_switch16x16;
7870	-- intstanciation et connexion du scheduler en fonction du nombre de ports
7871	-- le circuit genere depend du parametre generique nombre de ports
7872	-- switch 2 ports
7873	scheduler_switch2x2 : if number_of_ports = 2 generate
7874
7875	Scheduler2_2: Scheduler
7876	GENERIC MAP(number_of_ports => 2 )
7877	PORT MAP(
7878	Request => Request_signal,
7879	Fifo_full => fifo_out_full_signal,
7880	clk => clk,
7881	priority_rotation =>priority_rotation_signal,
7882	reset => reset,
7883	port_grant => grant_signal
7884	);
7885
7886	end generate scheduler_switch2x2;
7887
7888
7889	-- switch 3 ports
7890	scheduler_switch3x3 : if number_of_ports = 3 generate
7891
7892	Scheduler3_3: Scheduler
7893	GENERIC MAP(number_of_ports => 3 )
7894	PORT MAP(
7895	Request => Request_signal,
7896	Fifo_full => fifo_out_full_signal,
7897	clk => clk,
7898	priority_rotation =>priority_rotation_signal,
7899	reset => reset,
7900	port_grant => grant_signal
7901	);
7902
7903	end generate scheduler_switch3x3;
7904
7905
7906	-- switch 4 ports
7907	scheduler_switch4x4 : if number_of_ports = 4 generate
7908
7909	Scheduler4_4: Scheduler
7910	GENERIC MAP(number_of_ports => 4 )
7911	PORT MAP(
7912	Request => Request_signal,
7913	Fifo_full => fifo_out_full_signal,
7914	clk => clk,
7915	priority_rotation =>priority_rotation_signal,
7916	reset => reset,
7917	port_grant => grant_signal
7918	);
7919
7920	end generate scheduler_switch4x4;
7921
7922
7923	-- switch 5 ports
7924	scheduler_switch5x5 : if number_of_ports = 5 generate
7925
7926	Scheduler5_5: Scheduler
7927	GENERIC MAP(number_of_ports => 5 )
7928	PORT MAP(
7929	Request => Request_signal,
7930	Fifo_full => fifo_out_full_signal,
7931	clk => clk,
7932	priority_rotation =>priority_rotation_signal,
7933	reset => reset,
7934	port_grant => grant_signal
7935	);
7936
7937	end generate scheduler_switch5x5;
7938
7939
7940	-- switch 6 ports
7941	scheduler_switch6x6 : if number_of_ports = 6 generate
7942
7943	Scheduler6_6: Scheduler
7944	GENERIC MAP(number_of_ports => 6 )
7945	PORT MAP(
7946	Request => Request_signal,
7947	Fifo_full => fifo_out_full_signal,
7948	clk => clk,
7949	priority_rotation =>priority_rotation_signal,
7950	reset => reset,
7951	port_grant => grant_signal
7952	);
7953
7954	end generate scheduler_switch6x6;
7955
7956
7957	-- switch 7 ports
7958	scheduler_switch7x7 : if number_of_ports = 7 generate
7959
7960	Scheduler7_7: Scheduler
7961	GENERIC MAP(number_of_ports => 7 )
7962	PORT MAP(
7963	Request => Request_signal,
7964	Fifo_full => fifo_out_full_signal,
7965	clk => clk,
7966	priority_rotation =>priority_rotation_signal,
7967	reset => reset,
7968	port_grant => grant_signal
7969	);
7970
7971	end generate scheduler_switch7x7;
7972
7973
7974	-- switch 8 ports
7975	scheduler_switch8x8 : if number_of_ports = 8 generate
7976
7977	Scheduler8_8: Scheduler
7978	GENERIC MAP(number_of_ports => 8 )
7979	PORT MAP(
7980	Request => Request_signal,
7981	Fifo_full => fifo_out_full_signal,
7982	clk => clk,
7983	priority_rotation =>priority_rotation_signal,
7984	reset => reset,
7985	port_grant => grant_signal
7986	);
7987
7988	end generate scheduler_switch8x8;
7989
7990
7991	-- switch 9 ports
7992	scheduler_switch9x9 : if number_of_ports = 9 generate
7993
7994	Scheduler9_9: Scheduler
7995	GENERIC MAP(number_of_ports => 9 )
7996	PORT MAP(
7997	Request => Request_signal,
7998	Fifo_full => fifo_out_full_signal,
7999	clk => clk,
8000	priority_rotation =>priority_rotation_signal,
8001	reset => reset,
8002	port_grant => grant_signal
8003	);
8004
8005	end generate scheduler_switch9x9;
8006
8007
8008	-- switch 10 ports
8009	scheduler_switch10x10 : if number_of_ports = 10 generate
8010
8011	Scheduler10_10: Scheduler
8012	GENERIC MAP(number_of_ports => 10 )
8013	PORT MAP(
8014	Request => Request_signal,
8015	Fifo_full => fifo_out_full_signal,
8016	clk => clk,
8017	priority_rotation =>priority_rotation_signal,
8018	reset => reset,
8019	port_grant => grant_signal
8020	);
8021
8022	end generate scheduler_switch10x10;
8023
8024
8025	-- switch 11 ports
8026	scheduler_switch11x11 : if number_of_ports = 11 generate
8027
8028	Scheduler11_11: Scheduler
8029	GENERIC MAP(number_of_ports => 11 )
8030	PORT MAP(
8031	Request => Request_signal,
8032	Fifo_full => fifo_out_full_signal,
8033	clk => clk,
8034	priority_rotation =>priority_rotation_signal,
8035	reset => reset,
8036	port_grant => grant_signal
8037	);
8038
8039	end generate scheduler_switch11x11;
8040
8041
8042	-- switch 12 ports
8043	scheduler_switch12x12 : if number_of_ports = 12 generate
8044
8045	Scheduler12_12: Scheduler
8046	GENERIC MAP(number_of_ports => 12 )
8047	PORT MAP(
8048	Request => Request_signal,
8049	Fifo_full => fifo_out_full_signal,
8050	clk => clk,
8051	priority_rotation =>priority_rotation_signal,
8052	reset => reset,
8053	port_grant => grant_signal
8054	);
8055
8056	end generate scheduler_switch12x12;
8057
8058
8059	-- switch 13 ports
8060	scheduler_switch13x13 : if number_of_ports = 13 generate
8061
8062	Scheduler13_13: Scheduler
8063	GENERIC MAP(number_of_ports => 13 )
8064	PORT MAP(
8065	Request => Request_signal,
8066	Fifo_full => fifo_out_full_signal,
8067	clk => clk,
8068	priority_rotation =>priority_rotation_signal,
8069	reset => reset,
8070	port_grant => grant_signal
8071	);
8072
8073	end generate scheduler_switch13x13;
8074
8075
8076	-- switch 14 ports
8077	scheduler_switch14x14 : if number_of_ports = 14 generate
8078
8079	Scheduler14_14: Scheduler
8080	GENERIC MAP(number_of_ports => 14 )
8081	PORT MAP(
8082	Request => Request_signal,
8083	Fifo_full => fifo_out_full_signal,
8084	clk => clk,
8085	priority_rotation =>priority_rotation_signal,
8086	reset => reset,
8087	port_grant => grant_signal
8088	);
8089
8090	end generate scheduler_switch14x14;
8091
8092
8093	-- switch 15 ports
8094	scheduler_switch15x15 : if number_of_ports = 15 generate
8095
8096	Scheduler15_15: Scheduler
8097	GENERIC MAP(number_of_ports => 15 )
8098	PORT MAP(
8099	Request => Request_signal,
8100	Fifo_full => fifo_out_full_signal,
8101	clk => clk,
8102	priority_rotation =>priority_rotation_signal,
8103	reset => reset,
8104	port_grant => grant_signal
8105	);
8106
8107	end generate scheduler_switch15x15;
8108
8109
8110	-- switch 16 ports
8111	scheduler_switch16x16 : if number_of_ports = 16 generate
8112
8113	Scheduler16_16: Scheduler
8114	GENERIC MAP(number_of_ports => 16 )
8115	PORT MAP(
8116	Request => Request_signal,
8117	Fifo_full => fifo_out_full_signal,
8118	clk => clk,
8119	priority_rotation =>priority_rotation_signal,
8120	reset => reset,
8121	port_grant => grant_signal
8122	);
8123
8124	end generate scheduler_switch16x16;
8125
8126
8127
8128
8129
8130
8131
8132
8133	end Behavioral;
8134

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source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/SWITCH_GENERIQUE.vhd @ 69

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