source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/Scheduler4_4.vhi

Last change on this file was 22, checked in by rolagamo, 12 years ago
File size: 822 bytes
Line 
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2-- VHDL Instantiation Created from source file Scheduler4_4.vhd -- 13:38:35 06/19/2011
3--
4-- Notes:
5-- 1) This instantiation template has been automatically generated using types
6-- std_logic and std_logic_vector for the ports of the instantiated module
7-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
8
9        COMPONENT Scheduler4_4
10        PORT(
11                Request : IN std_logic_vector(16 downto 1);
12                Fifo_full : IN std_logic_vector(4 downto 1);
13                clk : IN std_logic;
14                reset : IN std_logic;
15                priority_rotation : IN std_logic_vector(4 downto 1);         
16                port_grant : OUT std_logic_vector(16 downto 1)
17                );
18        END COMPONENT;
19
20        Inst_Scheduler4_4: Scheduler4_4 PORT MAP(
21                Request => ,
22                Fifo_full => ,
23                clk => ,
24                reset => ,
25                priority_rotation => ,
26                port_grant =>
27        );
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