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proto_send.vhd

Last change on this file was 75, checked in by rolagamo, 11 years ago

File size: 5.5 KB

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1	----------------------------------------------------------------------------------
2	-- Company:
3	-- Engineer:
4	--
5	-- Create Date: 18:01:21 10/23/2012
6	-- Design Name:
7	-- Module Name: proto_send - Behavioral
8	-- Project Name:
9	-- Target Devices:
10	-- Tool versions:
11	-- Description:
12	--
13	-- Dependencies:
14	--
15	-- Revision:
16	-- Revision 0.01 - File Created
17	-- Additional Comments:
18	--
19	----------------------------------------------------------------------------------
20	library IEEE;
21	use IEEE.STD_LOGIC_1164.ALL;
22	USE ieee.numeric_std.ALL;
23	use work.CoreTypes.all;
24	-- Uncomment the following library declaration if using
25	-- arithmetic functions with Signed or Unsigned values
26	--use IEEE.NUMERIC_STD.ALL;
27
28	-- Uncomment the following library declaration if instantiating
29	-- any Xilinx primitives in this code.
30	--library UNISIM;
31	--use UNISIM.VComponents.all;
32
33	entity proto_send is
34	generic (sizemem : natural := 64);
35	port (
36	clk,reset : in std_logic;
37	fifo_in_empty,fifo_in_full : in std_logic; --signaux pour le fifo d'entrée
38	fifo_out_empty,fifo_out_full : in std_logic; --signaux pour le fifo de sortie
39	fifo_out_wr_en : out std_logic:='0'; --écriture autorisée dans la fifo de sortie
40	fifo_in_rd_en : out std_logic:='0'; --lecture autorisée dans la fifo d'entrée
41	fifo_in_data_out : in std_logic_vector(Word-1 downto 0);
42	fifo_out_data_in : out std_logic_vector(Word-1 downto 0);
43	packet_len : in std_logic_vector(Word-1 downto 0); --la longueur du paquet
44	copy_mode : in std_logic; --Fifo_to_mem ou Fifo_to_fifo
45	snd_start : in std_logic; --début de la réception
46	snd_ack :in std_logic; -- acquittement de la réception
47	snd_comp : out std_logic; -- fin de la réception
48	mem :in memory(0 to sizemem-1)); --données à copier vers le fifo
49
50	end proto_send;
51
52	architecture Behavioral of proto_send is
53	type typ_send is (s_head,s_len,s_len2,s_data,s_pulse,s_end);
54	signal etsnd : typ_send;
55	signal snd_state,next_snd_state:natural range 0 to 7:=0;
56	signal p_len,p_len_i : natural range 0 to 255;
57	signal n,n_i:natural range 0 to 7;
58	signal wr_ok,rd_ok:std_logic:='0';
59	signal wr_ok_i,rd_ok_i:std_logic:='0';
60	signal sfifo_in,Data_to_send,Data_to_send_i : std_logic_vector(Word-1 downto 0);
61	signal spush : std_logic:='0';
62	signal err : std_logic_vector(Word-1 downto 0):=(others =>'0');
63	begin
64
65	Fifo_copy_sync:process(clk,reset)
66
67	begin
68
69
70	if reset='1' then
71	n<=0;
72	Snd_state<=0;
73	P_len<=0;
74	Data_to_send<=(others=>'0');
75	else
76	if rising_edge(clk) then
77	Snd_state<=Next_Snd_state;
78	n<=n_i;
79	p_len<=P_len_i;
80	Data_to_send<=Data_to_send_i;
81	wr_ok<=wr_ok_i;
82	rd_ok<=rd_ok_i;
83	end if;
84	end if;
85	end process fifo_copy_sync;
86	-- affectation concurentes
87	Fifo_copy_val:process (Snd_state,Etsnd,copy_mode,data_to_send,rd_ok,wr_ok,spush)
88	begin
89	--fifo_out_wr_en<='0';
90	--fifo_in_rd_en<='0';
91	--fifo_out_data_in<=data_to_send;
92	if copy_mode='0' then
93	fifo_out_wr_en<=wr_ok;
94	fifo_out_data_in<=data_to_send;
95	fifo_in_rd_en<='0';
96	else
97	if (Snd_state=1) or (snd_state=2) then
98	fifo_out_wr_en<=wr_ok;
99	fifo_in_rd_en<=rd_ok;
100	fifo_out_data_in<=data_to_send;
101	end if;
102	end if;
103	end process fifo_copy_val;
104	-- process qui envoie des données en provenance d'un Fifo vers un Fifo
105	FIfo_to_fifo:process(snd_state,copy_mode,snd_start,snd_ack,fifo_in_empty,
106	fifo_out_full,Fifo_in_data_out,p_len,n,mem,wr_ok,rd_ok)
107	variable onepop:std_logic:='0';
108	begin
109	Next_snd_state<=snd_state; --valeur par defaut
110	Data_To_Send_i<=Data_to_send;
111	wr_ok_i<=wr_ok;
112	rd_ok_i<=rd_ok;
113	case snd_state is
114
115	when 0 => if snd_start='1' then
116	P_len_i<=to_integer(unsigned(packet_len));
117	next_snd_state<=1;
118	n_i<=0;
119	end if;
120	wr_ok_i<='0';rd_ok_i<='0';onepop:='0';
121	snd_comp<='0';
122	when 1=> --placer la première donnée sur le bus
123	if copy_mode='1' then
124	if fifo_in_empty='0' then
125	data_to_send_i <=fifo_in_data_out ;
126	end if;
127	else
128	data_to_send_i<=mem(n);
129	end if;
130	next_snd_state<=2;
131	when 2=> if P_len>0 then
132	if copy_mode='1' then
133	if fifo_in_empty='0' and onepop='0' then
134	data_to_send_i <=fifo_in_data_out ;
135	rd_Ok_i<='1';
136	onepop:='1'; --une donnée lue il faut arrêter de dépiler
137
138	else
139	rd_Ok_i<='0';
140	end if;
141	else
142	onepop:='1';rd_ok_i<='0'; --pas besoin de signal de lecture ici
143	data_to_send_i<=mem(n);
144	end if;
145
146	if (fifo_out_full = '0') and onepop='1' then
147	wr_ok_i<='1';
148	onepop:='0';
149	p_len_i<=p_len-1;
150	n_i<=n+1;
151	else
152	wr_Ok_i<='0';
153	end if;
154	else
155	rd_ok_i<='0';
156	wr_ok_i<='0';
157	next_snd_state<=3;
158	snd_comp<='1';
159	end if;
160	when 3 => --fin de la copie
161	if snd_ack='1' then
162
163	next_snd_state<=4;
164	end if;
165	wr_ok_i<='0';rd_ok_i<='0';
166	snd_comp<='1';
167
168	when 4 =>next_snd_state<=0;
169	snd_comp<='0';
170
171	when others => next_snd_state<=0;
172	snd_comp<='0';
173	rd_ok_i<='0';
174	wr_ok_i<='0';
175	data_to_send_i <=(others=>'U');
176	end case;
177	end process FIfo_to_fifo;
178
179	end Behavioral;
180

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source: PROJECT_CORE_MPI/SWITCH_GEN/BRANCHES/v0.03/proto_send.vhd

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