[22] | 1 | ---------------------------------------------------------------------------------- |
---|
| 2 | -- Company: |
---|
| 3 | -- Engineer: Kiegaing Emmanuel GEL EN5 |
---|
| 4 | -- |
---|
| 5 | -- Create Date: 18:18:09 03/19/2011 |
---|
| 6 | -- Design Name: |
---|
| 7 | -- Module Name: Arbiter - Behavioral |
---|
| 8 | -- Project Name: |
---|
| 9 | -- Target Devices: |
---|
| 10 | -- Tool versions: |
---|
| 11 | -- Description: |
---|
| 12 | -- cellule d'arbitrage de l'ordonnanceur du crossbar |
---|
| 13 | -- Dependencies: |
---|
| 14 | -- |
---|
| 15 | -- Revision: 1.0 |
---|
| 16 | -- a été ajouté le signal fifo_full pour inclure la codition buffer pas plein dans |
---|
| 17 | -- la cellules d'arbitrage |
---|
| 18 | -- Revision 0.01 - File Created |
---|
| 19 | -- Additional Comments: |
---|
| 20 | -- |
---|
| 21 | ---------------------------------------------------------------------------------- |
---|
| 22 | library IEEE; |
---|
| 23 | use IEEE.STD_LOGIC_1164.ALL; |
---|
| 24 | use IEEE.STD_LOGIC_ARITH.ALL; |
---|
| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
---|
| 26 | |
---|
| 27 | ---- Uncomment the following library declaration if instantiating |
---|
| 28 | ---- any Xilinx primitives in this code. |
---|
| 29 | --library UNISIM; |
---|
| 30 | --use UNISIM.VComponents.all; |
---|
| 31 | |
---|
| 32 | entity Arbiter is |
---|
| 33 | Port ( P: in STD_LOGIC;--vecteur de priorité |
---|
| 34 | Fifo_full : in STD_LOGIC; |
---|
| 35 | Request : in STD_LOGIC;-- demande de permission |
---|
| 36 | West : in STD_LOGIC;-- verouillage ouest |
---|
| 37 | North : in STD_LOGIC;--etc |
---|
| 38 | Grant : out STD_LOGIC;-- validation de la transition |
---|
| 39 | East : out STD_LOGIC; |
---|
| 40 | South : out STD_LOGIC); |
---|
| 41 | end Arbiter; |
---|
| 42 | |
---|
| 43 | architecture Behavioral of Arbiter is |
---|
| 44 | -- modelisation comportementale 3 LUT après synthèse |
---|
| 45 | -- ce module peut aussi facilement s'implémenter en flot de données |
---|
| 46 | signal grant_signal : STD_LOGIC; |
---|
| 47 | --signal not_fifo_full : STD_LOGIC; |
---|
| 48 | signal Mask : STD_LOGIC; |
---|
| 49 | begin |
---|
| 50 | --Grant<=grant_signal; -- Grant n'a pas été déclarée InOut |
---|
| 51 | Mask <= P AND (not Fifo_full); |
---|
| 52 | process(Mask, Request, North, West)-- genere de la logique purement combinatoire |
---|
| 53 | begin |
---|
| 54 | if Mask ='0' then --cellule inactive |
---|
| 55 | Grant <= '0';-- pas d'autorisation |
---|
| 56 | South <= '1'; |
---|
| 57 | East <= '1'; |
---|
| 58 | else |
---|
| 59 | Grant <= Request And North And West; |
---|
| 60 | South <= (North) And (Not (Request And North And West)); |
---|
| 61 | East <= (West) And (Not (Request And North And West)); |
---|
| 62 | end if; |
---|
| 63 | end process; |
---|
| 64 | |
---|
| 65 | end Behavioral; |
---|
| 66 | --modélidation flot de données elle semble plus efficace 3 LUT |
---|
| 67 | --architecture Behavioral of Arbiter is |
---|
| 68 | --signal x, x1, x2, x3, x4, x5: STD_LOGIC; |
---|
| 69 | --begin |
---|
| 70 | ----equations logiques de la cellule |
---|
| 71 | --x <= Mask And Request; |
---|
| 72 | --x1 <= North; |
---|
| 73 | --x2 <= West; |
---|
| 74 | --x3 <= x And x1 And x2; |
---|
| 75 | --x4 <= x1 And (Not x3); |
---|
| 76 | --x5 <= x2 And (Not x3); |
---|
| 77 | --South <= x4 Or (Not Mask); |
---|
| 78 | --East <= x5 Or (Not Mask); |
---|
| 79 | --Grant <= x3; |
---|
| 80 | -- |
---|
| 81 | --end Behavioral; |
---|
| 82 | |
---|
| 83 | |
---|