[20] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: Kiegaing Emmanuel GEL EN5 |
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| 4 | -- |
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| 5 | -- Create Date: 18:18:09 03/19/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Arbiter - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- cellule d'arbitrage de l'ordonnanceur du crossbar |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: 1.0 |
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| 16 | -- a été ajouté le signal fifo_full pour inclure la codition buffer pas plein dans |
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| 17 | -- la cellules d'arbitrage |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | ---------------------------------------------------------------------------------- |
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| 22 | library IEEE; |
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| 23 | use IEEE.STD_LOGIC_1164.ALL; |
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| 24 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | |
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| 27 | ---- Uncomment the following library declaration if instantiating |
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| 28 | ---- any Xilinx primitives in this code. |
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| 29 | --library UNISIM; |
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| 30 | --use UNISIM.VComponents.all; |
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| 31 | |
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| 32 | entity Arbiter is |
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| 33 | Port ( P: in STD_LOGIC;--vecteur de priorité |
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| 34 | Fifo_full : in STD_LOGIC; |
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| 35 | Request : in STD_LOGIC;-- demande de permission |
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| 36 | West : in STD_LOGIC;-- verouillage ouest |
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| 37 | North : in STD_LOGIC;--etc |
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| 38 | Grant : out STD_LOGIC;-- validation de la transition |
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| 39 | East : out STD_LOGIC; |
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| 40 | South : out STD_LOGIC); |
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| 41 | end Arbiter; |
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| 42 | |
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| 43 | architecture Behavioral of Arbiter is |
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| 44 | -- modelisation comportementale 3 LUT après synthèse |
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| 45 | -- ce module peut aussi facilement s'implémenter en flot de données |
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| 46 | signal grant_signal : STD_LOGIC; |
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| 47 | --signal not_fifo_full : STD_LOGIC; |
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| 48 | signal Mask : STD_LOGIC; |
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| 49 | begin |
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| 50 | --Grant<=grant_signal; -- Grant n'a pas été déclarée InOut |
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| 51 | Mask <= P AND (not Fifo_full); |
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| 52 | process(Mask, Request, North, West)-- genere de la logique purement combinatoire |
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| 53 | begin |
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| 54 | if Mask ='0' then --cellule inactive |
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| 55 | Grant <= '0';-- pas d'autorisation |
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| 56 | South <= '1'; |
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| 57 | East <= '1'; |
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| 58 | else |
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| 59 | Grant <= Request And North And West; |
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| 60 | South <= (North) And (Not (Request And North And West)); |
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| 61 | East <= (West) And (Not (Request And North And West)); |
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| 62 | end if; |
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| 63 | end process; |
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| 64 | |
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| 65 | end Behavioral; |
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| 66 | --modélidation flot de données elle semble plus efficace 3 LUT |
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| 67 | --architecture Behavioral of Arbiter is |
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| 68 | --signal x, x1, x2, x3, x4, x5: STD_LOGIC; |
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| 69 | --begin |
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| 70 | ----equations logiques de la cellule |
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| 71 | --x <= Mask And Request; |
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| 72 | --x1 <= North; |
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| 73 | --x2 <= West; |
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| 74 | --x3 <= x And x1 And x2; |
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| 75 | --x4 <= x1 And (Not x3); |
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| 76 | --x5 <= x2 And (Not x3); |
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| 77 | --South <= x4 Or (Not Mask); |
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| 78 | --East <= x5 Or (Not Mask); |
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| 79 | --Grant <= x3; |
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| 80 | -- |
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| 81 | --end Behavioral; |
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| 82 | |
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| 83 | |
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