[17] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: |
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| 4 | -- |
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| 5 | -- Create Date: 16:32:59 10/23/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: FIFO_DP - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | |
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| 21 | library IEEE; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | |
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| 26 | entity fifo_dp is |
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| 27 | GENERIC |
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| 28 | ( |
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| 29 | ADDRESS_WIDTH : integer:=8;---8 bit |
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| 30 | DATA_WIDTH : integer:=8 ---8 bit |
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| 31 | ); |
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| 32 | |
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| 33 | port ( clk : in std_logic; |
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| 34 | reset : in std_logic; |
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| 35 | enr : in std_logic; --enable read,should be '0' when not in use. |
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| 36 | enw : in std_logic; --enable write,should be '0' when not in use. |
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| 37 | dataout : out std_logic_vector(DATA_WIDTH-1 downto 0); --output data |
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| 38 | datain : in std_logic_vector (DATA_WIDTH-1 downto 0); --input data |
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| 39 | empty : out std_logic; --set as '1' when the queue is empty |
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| 40 | err : out std_logic; |
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| 41 | full : out std_logic --set as '1' when the queue is full |
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| 42 | ); |
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| 43 | end fifo; |
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| 44 | |
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| 45 | architecture Behavioral of fifo_dp is |
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| 46 | |
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| 47 | type memory_type is array (0 to ((2**ADDRESS_WIDTH)-1)) of std_logic_vector(DATA_WIDTH-1 downto 0); |
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| 48 | |
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| 49 | |
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| 50 | -----distributed------- |
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| 51 | signal memory : memory_type ;-- :=(others => (others => '0')); --memory for queue.----- |
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| 52 | signal readptr,writeptr : std_logic_vector(ADDRESS_WIDTH-1 downto 0); --read and write pointers. |
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| 53 | signal full0 : std_logic; |
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| 54 | signal empty0 : std_logic; |
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| 55 | |
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| 56 | begin |
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| 57 | full <= full0; |
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| 58 | empty <= empty0; |
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| 59 | |
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| 60 | fifo0: process(clk,reset) |
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| 61 | begin |
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| 62 | if reset='1' then |
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| 63 | |
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| 64 | readptr <= (others => '0'); |
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| 65 | writeptr <= (others => '0'); |
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| 66 | empty0 <='1'; |
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| 67 | full0<='0'; |
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| 68 | err<='0'; |
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| 69 | |
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| 70 | |
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| 71 | elsif rising_edge(clk) then |
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| 72 | |
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| 73 | if (writeptr + '1' = readptr) then |
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| 74 | full0<='1'; |
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| 75 | else |
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| 76 | full0<='0'; |
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| 77 | end if ; |
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| 78 | |
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| 79 | if (readptr = writeptr ) then |
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| 80 | empty0<='1'; |
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| 81 | else |
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| 82 | empty0<='0'; |
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| 83 | end if ; |
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| 84 | |
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| 85 | if (empty0='0' and enr='1') or (full0='0' and enw='1') then |
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| 86 | err<='1'; |
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| 87 | end if ; |
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| 88 | |
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| 89 | if enw='1' and full0='0' then |
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| 90 | memory (conv_integer(writeptr)) <= datain ; |
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| 91 | writeptr <= writeptr + '1' ; |
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| 92 | end if ; |
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| 93 | |
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| 94 | if enr='1' and empty0='0' then |
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| 95 | dataout <= memory (conv_integer(readptr)); |
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| 96 | readptr <= readptr + '1' ; |
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| 97 | end if ; |
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| 98 | |
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| 99 | end if; |
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| 100 | |
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| 101 | end process; |
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| 102 | end Behavioral; |
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