source: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/GENERIC_16_16.xise

Last change on this file was 22, checked in by rolagamo, 12 years ago
File size: 43.9 KB
Line 
1<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4  <header>
5    <!-- ISE source project file created by Project Navigator.             -->
6    <!--                                                                   -->
7    <!-- This file contains project source information including a list of -->
8    <!-- project source files, project and process properties.  This file, -->
9    <!-- along with the project source files, is sufficient to open and    -->
10    <!-- implement in ISE Project Navigator.                               -->
11    <!--                                                                   -->
12    <!-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved. -->
13  </header>
14
15  <version xil_pn:ise_version="12.3" xil_pn:schema_version="2"/>
16
17  <files>
18    <file xil_pn:name="Crossbit.vhd" xil_pn:type="FILE_VHDL">
19      <association xil_pn:name="BehavioralSimulation"/>
20      <association xil_pn:name="Implementation"/>
21    </file>
22    <file xil_pn:name="Crossbar.vhd" xil_pn:type="FILE_VHDL">
23      <association xil_pn:name="BehavioralSimulation"/>
24      <association xil_pn:name="Implementation"/>
25    </file>
26    <file xil_pn:name="Scheduler.vhd" xil_pn:type="FILE_VHDL">
27      <association xil_pn:name="BehavioralSimulation"/>
28      <association xil_pn:name="Implementation"/>
29    </file>
30    <file xil_pn:name="Arbiter.vhd" xil_pn:type="FILE_VHDL">
31      <association xil_pn:name="BehavioralSimulation"/>
32      <association xil_pn:name="Implementation"/>
33    </file>
34    <file xil_pn:name="SCHEDULER2_2.VHD" xil_pn:type="FILE_VHDL">
35      <association xil_pn:name="BehavioralSimulation"/>
36      <association xil_pn:name="Implementation"/>
37    </file>
38    <file xil_pn:name="SCHEDULER3_3.VHD" xil_pn:type="FILE_VHDL">
39      <association xil_pn:name="BehavioralSimulation"/>
40      <association xil_pn:name="Implementation"/>
41    </file>
42    <file xil_pn:name="SCHEDULER4_4.VHD" xil_pn:type="FILE_VHDL">
43      <association xil_pn:name="BehavioralSimulation"/>
44      <association xil_pn:name="Implementation"/>
45    </file>
46    <file xil_pn:name="SCHEDULER5_5.VHD" xil_pn:type="FILE_VHDL">
47      <association xil_pn:name="BehavioralSimulation"/>
48      <association xil_pn:name="Implementation"/>
49    </file>
50    <file xil_pn:name="SCHEDULER6_6.VHD" xil_pn:type="FILE_VHDL">
51      <association xil_pn:name="BehavioralSimulation"/>
52      <association xil_pn:name="Implementation"/>
53    </file>
54    <file xil_pn:name="SCHEDULER7_7.VHD" xil_pn:type="FILE_VHDL">
55      <association xil_pn:name="BehavioralSimulation"/>
56      <association xil_pn:name="Implementation"/>
57    </file>
58    <file xil_pn:name="SCHEDULER8_8.VHD" xil_pn:type="FILE_VHDL">
59      <association xil_pn:name="BehavioralSimulation"/>
60      <association xil_pn:name="Implementation"/>
61    </file>
62    <file xil_pn:name="SCHEDULER9_9.VHD" xil_pn:type="FILE_VHDL">
63      <association xil_pn:name="BehavioralSimulation"/>
64      <association xil_pn:name="Implementation"/>
65    </file>
66    <file xil_pn:name="SCHEDULER10_10.VHD" xil_pn:type="FILE_VHDL">
67      <association xil_pn:name="BehavioralSimulation"/>
68      <association xil_pn:name="Implementation"/>
69    </file>
70    <file xil_pn:name="SCHEDULER11_11.VHD" xil_pn:type="FILE_VHDL">
71      <association xil_pn:name="BehavioralSimulation"/>
72      <association xil_pn:name="Implementation"/>
73    </file>
74    <file xil_pn:name="SCHEDULER12_12.VHD" xil_pn:type="FILE_VHDL">
75      <association xil_pn:name="BehavioralSimulation"/>
76      <association xil_pn:name="Implementation"/>
77    </file>
78    <file xil_pn:name="SCHEDULER13_13.VHD" xil_pn:type="FILE_VHDL">
79      <association xil_pn:name="BehavioralSimulation"/>
80      <association xil_pn:name="Implementation"/>
81    </file>
82    <file xil_pn:name="SCHEDULER14_14.VHD" xil_pn:type="FILE_VHDL">
83      <association xil_pn:name="BehavioralSimulation"/>
84      <association xil_pn:name="Implementation"/>
85    </file>
86    <file xil_pn:name="SCHEDULER15_15.VHD" xil_pn:type="FILE_VHDL">
87      <association xil_pn:name="BehavioralSimulation"/>
88      <association xil_pn:name="Implementation"/>
89    </file>
90    <file xil_pn:name="SCHEDULER16_16.VHD" xil_pn:type="FILE_VHDL">
91      <association xil_pn:name="BehavioralSimulation"/>
92      <association xil_pn:name="Implementation"/>
93    </file>
94    <file xil_pn:name="RAM_256.vhd" xil_pn:type="FILE_VHDL">
95      <association xil_pn:name="BehavioralSimulation"/>
96      <association xil_pn:name="Implementation"/>
97    </file>
98    <file xil_pn:name="FIFO_256_FWFT.vhd" xil_pn:type="FILE_VHDL">
99      <association xil_pn:name="BehavioralSimulation"/>
100      <association xil_pn:name="Implementation"/>
101    </file>
102    <file xil_pn:name="INPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
103      <association xil_pn:name="BehavioralSimulation"/>
104      <association xil_pn:name="Implementation"/>
105    </file>
106    <file xil_pn:name="OUTPUT_PORT_MODULE.vhd" xil_pn:type="FILE_VHDL">
107      <association xil_pn:name="BehavioralSimulation"/>
108      <association xil_pn:name="Implementation"/>
109    </file>
110    <file xil_pn:name="SWITCH_GENERIQUE.vhd" xil_pn:type="FILE_VHDL">
111      <association xil_pn:name="BehavioralSimulation"/>
112      <association xil_pn:name="Implementation"/>
113    </file>
114    <file xil_pn:name="test_xbar_8x8.vhd" xil_pn:type="FILE_VHDL">
115      <association xil_pn:name="BehavioralSimulation"/>
116      <association xil_pn:name="PostMapSimulation"/>
117      <association xil_pn:name="PostRouteSimulation"/>
118      <association xil_pn:name="PostTranslateSimulation"/>
119    </file>
120    <file xil_pn:name="conv.vhd" xil_pn:type="FILE_VHDL">
121      <association xil_pn:name="BehavioralSimulation"/>
122      <association xil_pn:name="Implementation"/>
123    </file>
124    <file xil_pn:name="stimuli1.vhd" xil_pn:type="FILE_VHDL">
125      <association xil_pn:name="BehavioralSimulation"/>
126      <association xil_pn:name="Implementation"/>
127    </file>
128    <file xil_pn:name="C:/RomSwitch/testport5.vhd" xil_pn:type="FILE_VHDL">
129      <association xil_pn:name="BehavioralSimulation"/>
130      <association xil_pn:name="Implementation"/>
131    </file>
132    <file xil_pn:name="SWITCH_GEN.vhd" xil_pn:type="FILE_VHDL">
133      <association xil_pn:name="BehavioralSimulation"/>
134      <association xil_pn:name="Implementation"/>
135    </file>
136    <file xil_pn:name="CoreTypes.vhd" xil_pn:type="FILE_VHDL">
137      <association xil_pn:name="BehavioralSimulation"/>
138      <association xil_pn:name="Implementation"/>
139    </file>
140    <file xil_pn:name="../CORE_MPI/sim_fifo.vhd" xil_pn:type="FILE_VHDL">
141      <association xil_pn:name="BehavioralSimulation"/>
142      <association xil_pn:name="Implementation"/>
143    </file>
144    <file xil_pn:name="Proto_receiv.vhd" xil_pn:type="FILE_VHDL">
145      <association xil_pn:name="BehavioralSimulation"/>
146      <association xil_pn:name="Implementation"/>
147    </file>
148    <file xil_pn:name="FIFO_DP.vhd" xil_pn:type="FILE_VHDL">
149      <association xil_pn:name="BehavioralSimulation"/>
150      <association xil_pn:name="Implementation"/>
151    </file>
152    <file xil_pn:name="proto_send.vhd" xil_pn:type="FILE_VHDL">
153      <association xil_pn:name="BehavioralSimulation"/>
154      <association xil_pn:name="Implementation"/>
155    </file>
156  </files>
157
158  <properties>
159    <property xil_pn:name="AES Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
160    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
161    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
162    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
163    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
164    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
165    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
166    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
167    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
168    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
169    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
170    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
171    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
172    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
173    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
174    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
175    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
176    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
177    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
178    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
179    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
180    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
181    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
182    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
183    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
184    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
185    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
186    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
187    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
188    <property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
189    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
190    <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
191    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
192    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
193    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
194    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
195    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
196    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
197    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
198    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
199    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
200    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
201    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
202    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
203    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
204    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
205    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
206    <property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="Test_fifo.wcfg" xil_pn:valueState="non-default"/>
207    <property xil_pn:name="Custom Waveform Configuration File Translate" xil_pn:value="test_xbar_8x8.wcfg" xil_pn:valueState="non-default"/>
208    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
209    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
210    <property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
211    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
212    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
213    <property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
214    <property xil_pn:name="Device" xil_pn:value="xc3s1200e" xil_pn:valueState="non-default"/>
215    <property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
216    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
217    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
218    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
219    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
220    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
221    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
222    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
223    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
224    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
225    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
226    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
227    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
228    <property xil_pn:name="Encrypt Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
229    <property xil_pn:name="Equivalent Register Removal" xil_pn:value="true" xil_pn:valueState="default"/>
230    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
231    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
232    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
233    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
234    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
235    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
236    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
237    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
238    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
239    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
240    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
241    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
242    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
243    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
244    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
245    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
246    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
247    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
248    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
249    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
250    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
251    <property xil_pn:name="Generate Detailed Package Parasitics" xil_pn:value="false" xil_pn:valueState="default"/>
252    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="true" xil_pn:valueState="non-default"/>
253    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
254    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="true" xil_pn:valueState="non-default"/>
255    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
256    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
257    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
258    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
259    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
260    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
261    <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
262    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
263    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
264    <property xil_pn:name="Global Optimization map" xil_pn:value="Off" xil_pn:valueState="default"/>
265    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
266    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
267    <property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
268    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
269    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
270    <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
271    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
272    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
273    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
274    <property xil_pn:name="Implementation Top File" xil_pn:value="../CORE_MPI/sim_fifo.vhd" xil_pn:valueState="non-default"/>
275    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
276    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
277    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
278    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
279    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
280    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
281    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
282    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
283    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
284    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
285    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
286    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
287    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
288    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
289    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
290    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
291    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
292    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
293    <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
294    <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
295    <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
296    <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
297    <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
298    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
299    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
300    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
301    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
302    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
303    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
304    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
305    <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
306    <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
307    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
308    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
309    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
310    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
311    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
312    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
313    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
314    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
315    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
316    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
317    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
318    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
319    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
320    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
321    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
322    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
323    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
324    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
325    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
326    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
327    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
328    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
329    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
330    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
331    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
332    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
333    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
334    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
335    <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
336    <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
337    <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
338    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
339    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
340    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
341    <property xil_pn:name="Output File Name" xil_pn:value="testbench" xil_pn:valueState="default"/>
342    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
343    <property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
344    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
345    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
346    <property xil_pn:name="Package" xil_pn:value="ft256" xil_pn:valueState="default"/>
347    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
348    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
349    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
350    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
351    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
352    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
353    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
354    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="testbench_map.vhd" xil_pn:valueState="default"/>
355    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="testbench_timesim.vhd" xil_pn:valueState="default"/>
356    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="testbench_synthesis.vhd" xil_pn:valueState="default"/>
357    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="testbench_translate.vhd" xil_pn:valueState="default"/>
358    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
359    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
360    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
361    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
362    <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
363    <property xil_pn:name="Produce Advanced Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
364    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
365    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
366    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
367    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
368    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
369    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
370    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
371    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
372    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
373    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
374    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
375    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
376    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
377    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
378    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
379    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="testbench" xil_pn:valueState="default"/>
380    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
381    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
382    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
383    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
384    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
385    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
386    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
387    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
388    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
389    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
390    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
391    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
392    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
393    <property xil_pn:name="Retiming" xil_pn:value="false" xil_pn:valueState="default"/>
394    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
395    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
396    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
397    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
398    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
399    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
400    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
401    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
402    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
403    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
404    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="non-default"/>
405    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
406    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="work.test_xbar_16x16" xil_pn:valueState="non-default"/>
407    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
408    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
409    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
410    <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
411    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
412    <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
413    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="180 ns" xil_pn:valueState="non-default"/>
414    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
415    <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
416    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
417    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
418    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
419    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
420    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
421    <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
422    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
423    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
424    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="work.test_xbar_8x8" xil_pn:valueState="default"/>
425    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
426    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="work.test_xbar_16x16" xil_pn:valueState="default"/>
427    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
428    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
429    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
430    <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
431    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
432    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
433    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
434    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
435    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
436    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
437    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
438    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
439    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
440    <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
441    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
442    <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
443    <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
444    <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
445    <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
446    <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
447    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
448    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
449    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
450    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
451    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
452    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
453    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
454    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
455    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
456    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
457    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
458    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="true" xil_pn:valueState="non-default"/>
459    <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
460    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
461    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
462    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
463    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
464    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
465    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
466    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="d:/Xilinx/12.3/ISE_DS/ISE/data/default.xds" xil_pn:valueState="non-default"/>
467    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
468    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
469    <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
470    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
471    <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
472    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
473    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
474    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
475    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
476    <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
477    <property xil_pn:name="Waveform Database Filename Post-Translate" xil_pn:value="test_xbar_8x8_isim_beh.wdb" xil_pn:valueState="non-default"/>
478    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
479    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
480    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
481    <!--                                                                                  -->
482    <!-- The following properties are for internal use only. These should not be modified.-->
483    <!--                                                                                  -->
484    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|testbench|behavior" xil_pn:valueState="non-default"/>
485    <property xil_pn:name="PROP_DesignName" xil_pn:value="GENERIC_16_16" xil_pn:valueState="non-default"/>
486    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
487    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
488    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="Architecture|test_xbar_16x16|behavior" xil_pn:valueState="non-default"/>
489    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
490    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
491    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="Architecture|test_xbar_16x16|behavior" xil_pn:valueState="non-default"/>
492    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
493    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-07-11T16:58:22" xil_pn:valueState="non-default"/>
494    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6E6D9310BD824CB7AA37132338EEB7D5" xil_pn:valueState="non-default"/>
495    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
496    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
497  </properties>
498
499  <bindings/>
500
501  <libraries>
502    <library xil_pn:name="NoClib"/>
503    <library xil_pn:name="typesconv"/>
504  </libraries>
505
506  <autoManagedFiles>
507    <!-- The following files are identified by `include statements in verilog -->
508    <!-- source files and are automatically managed by Project Navigator.     -->
509    <!--                                                                      -->
510    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
511    <!-- project is analyzed based on files automatically identified as       -->
512    <!-- include files.                                                       -->
513  </autoManagedFiles>
514
515</project>
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