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| 2 | -- VHDL Instantiation Created from source file INPUT_PORT_MODULE.vhd -- 15:22:33 06/19/2011 |
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| 3 | -- |
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| 4 | -- Notes: |
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| 5 | -- 1) This instantiation template has been automatically generated using types |
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| 6 | -- std_logic and std_logic_vector for the ports of the instantiated module |
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| 7 | -- 2) To use this template to instantiate this entity, cut-and-paste and then edit |
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| 8 | |
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| 9 | COMPONENT INPUT_PORT_MODULE |
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| 10 | PORT( |
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| 11 | data_in : IN std_logic_vector(7 downto 0); |
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| 12 | data_in_en : IN std_logic; |
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| 13 | reset : IN std_logic; |
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| 14 | clk : IN std_logic; |
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| 15 | grant : IN std_logic_vector(4 downto 1); |
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| 16 | request : OUT std_logic_vector(4 downto 1); |
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| 17 | fifo_full : OUT std_logic; |
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| 18 | fifo_empty : OUT std_logic; |
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| 19 | priority_rotation : OUT std_logic; |
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| 20 | data_out : OUT std_logic_vector(7 downto 0); |
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| 21 | data_out_pulse : OUT std_logic |
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| 22 | ); |
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| 23 | END COMPONENT; |
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| 24 | |
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| 25 | Inst_INPUT_PORT_MODULE: INPUT_PORT_MODULE PORT MAP( |
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| 26 | data_in => , |
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| 27 | data_in_en => , |
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| 28 | reset => , |
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| 29 | clk => , |
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| 30 | request => , |
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| 31 | grant => , |
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| 32 | fifo_full => , |
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| 33 | fifo_empty => , |
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| 34 | priority_rotation => , |
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| 35 | data_out => , |
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| 36 | data_out_pulse => |
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| 37 | ); |
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| 38 | |
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| 39 | |
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