source: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.vhi

Last change on this file was 22, checked in by rolagamo, 12 years ago
File size: 1.1 KB
Line 
1
2-- VHDL Instantiation Created from source file INPUT_PORT_MODULE.vhd -- 15:22:33 06/19/2011
3--
4-- Notes:
5-- 1) This instantiation template has been automatically generated using types
6-- std_logic and std_logic_vector for the ports of the instantiated module
7-- 2) To use this template to instantiate this entity, cut-and-paste and then edit
8
9        COMPONENT INPUT_PORT_MODULE
10        PORT(
11                data_in : IN std_logic_vector(7 downto 0);
12                data_in_en : IN std_logic;
13                reset : IN std_logic;
14                clk : IN std_logic;
15                grant : IN std_logic_vector(4 downto 1);         
16                request : OUT std_logic_vector(4 downto 1);
17                fifo_full : OUT std_logic;
18                fifo_empty : OUT std_logic;
19                priority_rotation : OUT std_logic;
20                data_out : OUT std_logic_vector(7 downto 0);
21                data_out_pulse : OUT std_logic
22                );
23        END COMPONENT;
24
25        Inst_INPUT_PORT_MODULE: INPUT_PORT_MODULE PORT MAP(
26                data_in => ,
27                data_in_en => ,
28                reset => ,
29                clk => ,
30                request => ,
31                grant => ,
32                fifo_full => ,
33                fifo_empty => ,
34                priority_rotation => ,
35                data_out => ,
36                data_out_pulse =>
37        );
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