source: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/INPUT_PORT_MODULE.xst

Last change on this file was 22, checked in by rolagamo, 12 years ago
File size: 1.1 KB
Line 
1set -tmpdir "xst/projnav.tmp"
2set -xsthdpdir "xst"
3run
4-ifn INPUT_PORT_MODULE.prj
5-ifmt mixed
6-ofn INPUT_PORT_MODULE
7-ofmt NGC
8-p xc3s1200e-4-fg320
9-top INPUT_PORT_MODULE
10-opt_mode Speed
11-opt_level 1
12-iuc NO
13-lso INPUT_PORT_MODULE.lso
14-keep_hierarchy NO
15-netlist_hierarchy as_optimized
16-rtlview Yes
17-glob_opt AllClockNets
18-read_cores YES
19-write_timing_constraints NO
20-cross_clock_analysis NO
21-hierarchy_separator /
22-bus_delimiter <>
23-case maintain
24-slice_utilization_ratio 100
25-bram_utilization_ratio 100
26-verilog2001 YES
27-fsm_extract YES -fsm_encoding Auto
28-safe_implementation No
29-fsm_style lut
30-ram_extract Yes
31-ram_style Auto
32-rom_extract Yes
33-mux_style Auto
34-decoder_extract YES
35-priority_extract YES
36-shreg_extract YES
37-shift_extract YES
38-xor_collapse YES
39-rom_style Auto
40-auto_bram_packing NO
41-mux_extract YES
42-resource_sharing YES
43-async_to_sync NO
44-iobuf YES
45-bufg 24
46-register_duplication YES
47-register_balancing No
48-slice_packing YES
49-optimize_primitives NO
50-use_clock_enable Yes
51-use_sync_set Yes
52-use_sync_reset Yes
53-iob auto
54-equivalent_register_removal YES
55-slice_utilization_ratio_maxmargin 5
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