[20] | 1 | |
---|
| 2 | ---------------------------------------------------------------------------------- |
---|
| 3 | -- Company: |
---|
| 4 | -- Engineer: |
---|
| 5 | -- |
---|
| 6 | -- Create Date: 09:29:48 04/18/2011 |
---|
| 7 | -- Design Name: |
---|
| 8 | -- Module Name: OUTPUT_PORT_MODULE - Behavioral_description |
---|
| 9 | -- Project Name: |
---|
| 10 | -- Target Devices: |
---|
| 11 | -- Tool versions: |
---|
| 12 | -- Description: |
---|
| 13 | -- cette version du module de sortie se limite à une instance du fifo ordinaire |
---|
| 14 | -- les données son emise en sortie à chaque cycle d'horloge |
---|
| 15 | -- Dependencies: |
---|
| 16 | -- |
---|
| 17 | -- Revision: |
---|
| 18 | -- Revision 0.01 - File Created |
---|
| 19 | -- Additional Comments: |
---|
| 20 | -- |
---|
| 21 | ---------------------------------------------------------------------------------- |
---|
| 22 | library IEEE; |
---|
| 23 | use IEEE.STD_LOGIC_1164.ALL; |
---|
| 24 | use IEEE.STD_LOGIC_ARITH.ALL; |
---|
| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
---|
| 26 | Library NocLib; |
---|
| 27 | use NocLib.CoreTypes.all; |
---|
| 28 | ---- Uncomment the following library declaration if instantiating |
---|
| 29 | ---- any Xilinx primitives in this code. |
---|
| 30 | --library UNISIM; |
---|
| 31 | --use UNISIM.VComponents.all; |
---|
| 32 | |
---|
| 33 | entity OUTPUT_PORT_MODULE is |
---|
| 34 | Port ( data_in : in STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 35 | reset : in STD_LOGIC; |
---|
| 36 | clk : in STD_LOGIC; |
---|
| 37 | wr_en : in STD_LOGIC; |
---|
| 38 | data_out : out STD_LOGIC_VECTOR (Word-1 downto 0); |
---|
| 39 | fifo_full : out std_logic; |
---|
| 40 | data_avalaible : out std_logic; |
---|
| 41 | rd_out_en : in STD_LOGIC); |
---|
| 42 | end OUTPUT_PORT_MODULE; |
---|
| 43 | |
---|
| 44 | architecture Behavioral_description of OUTPUT_PORT_MODULE is |
---|
| 45 | -- declaration du FIFO 64 octets |
---|
| 46 | component FIFO_256_FWFT |
---|
| 47 | port ( |
---|
| 48 | clk: IN std_logic; |
---|
| 49 | din: IN std_logic_VECTOR(Word-1 downto 0); |
---|
| 50 | rd_en: IN std_logic; |
---|
| 51 | srst: IN std_logic; |
---|
| 52 | wr_en: IN std_logic; |
---|
| 53 | dout: OUT std_logic_VECTOR(Word-1 downto 0); |
---|
| 54 | empty: OUT std_logic; |
---|
| 55 | full: OUT std_logic); |
---|
| 56 | end component; |
---|
| 57 | --definition du type etat pour les fsm |
---|
| 58 | signal empty_signal : std_logic; |
---|
| 59 | begin |
---|
| 60 | -- instantiation du FIFO_64 |
---|
| 61 | OUTPUT_PORT_FIFO : FIFO_256_FWFT |
---|
| 62 | port map ( |
---|
| 63 | clk => clk, |
---|
| 64 | din => data_in, |
---|
| 65 | rd_en => rd_out_en, |
---|
| 66 | srst => reset, |
---|
| 67 | wr_en => wr_en, |
---|
| 68 | dout => data_out, |
---|
| 69 | empty => empty_signal, |
---|
| 70 | full => fifo_full); |
---|
| 71 | |
---|
| 72 | data_avalaible <= not empty_signal; |
---|
| 73 | |
---|
| 74 | end Behavioral_description; |
---|
| 75 | |
---|