[17] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: GAMOM NGOUNOU ROland Christian |
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| 4 | -- |
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| 5 | -- Create Date: 12:49:02 02/02/2012 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Portdata - arch_portdata |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: |
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| 12 | -- |
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| 13 | -- Dependencies: |
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| 14 | -- |
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| 15 | -- Revision: |
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| 16 | -- Revision 0.01 - File Created |
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| 17 | -- Additional Comments: |
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| 18 | -- |
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| 19 | ---------------------------------------------------------------------------------- |
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| 20 | library IEEE; |
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| 21 | use IEEE.STD_LOGIC_1164.ALL; |
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| 22 | |
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| 23 | -- Uncomment the following library declaration if using |
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| 24 | -- arithmetic functions with Signed or Unsigned values |
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| 25 | use ieee.numeric_std.all; |
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| 26 | --USE ieee.std_logic_arith.all; |
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| 27 | |
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| 28 | |
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| 29 | entity Portdata is |
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| 30 | generic (N:Natural:=8); |
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| 31 | Port ( clk : in STD_LOGIC; |
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| 32 | reset : in STD_LOGIC; |
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| 33 | wr_en : in STD_LOGIC; |
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| 34 | rd_en : in STD_LOGIC; |
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| 35 | datain : in STD_LOGIC_VECTOR (N-1 downto 0); |
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| 36 | dataout : out STD_LOGIC_VECTOR (N-1 downto 0); |
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| 37 | address : in STD_LOGIC_VECTOR (3 downto 0)); |
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| 38 | end Portdata; |
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| 39 | |
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| 40 | architecture arch_portdata of Portdata is |
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| 41 | |
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| 42 | Type Ram_type is array (0 to 3) of std_logic_vector (N-1 downto 0); |
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| 43 | constant zero : integer :=0; |
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| 44 | constant Zero_log:STD_LOGIC_VECTOR:=STD_LOGIC_VECTOR(to_unsigned(zero,N)); |
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| 45 | constant portid:STD_LOGIC_VECTOR:="00000001"; |
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| 46 | signal RAM : Ram_type; |
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| 47 | |
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| 48 | constant max_address : natural:=15; |
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| 49 | signal address_counter : natural := 0; |
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| 50 | begin |
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| 51 | |
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| 52 | dataout <= RAM(address_counter); |
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| 53 | process (clk) |
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| 54 | begin |
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| 55 | if rising_edge(clk) then |
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| 56 | if reset = '1' then |
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| 57 | address_counter <= 0; |
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| 58 | for address_counter in 1 to max_address --la mémoire d'adresse 0 contient |
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| 59 | loop -- l'ID du port |
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| 60 | RAM(address_counter)<=(others=>'0'); |
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| 61 | end loop; |
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| 62 | RAM(0)<=portid; -- portid est une valeur fixé par le générateur de port |
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| 63 | elsif rd_en='1' and wr_en='0' then |
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| 64 | |
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| 65 | RAM(to_integer(unsigned(address)))<=datain; |
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| 66 | |
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| 67 | elsif rd_en='0' and wr_en='1' then |
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| 68 | dataout <= RAM(to_integer(unsigned(address))); |
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| 69 | |
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| 70 | end if; |
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| 71 | end if; |
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| 72 | end process; |
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| 73 | end arch_portdata; |
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| 74 | |
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