[22] | 1 | --------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL GEL EN 5 |
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| 4 | -- |
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| 5 | -- Create Date: 03:56:34 05/06/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Sheduler - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Module de l'ordonnanceur du switch crossbar |
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| 12 | -- l'algorithme utilisée est le DPA (diagonal propagation arbiter) |
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| 13 | -- |
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| 14 | -- Dependencies: |
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| 15 | -- |
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| 16 | -- Revision: |
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| 17 | -- Revision 0.01 - File Created |
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| 18 | -- Additional Comments: |
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| 19 | -- |
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| 20 | ---------------------------------------------------------------------------------- |
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| 21 | library IEEE; |
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| 22 | use IEEE.STD_LOGIC_1164.ALL; |
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| 23 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 24 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 25 | --use Work.Sheduler_package.all; |
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| 26 | |
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| 27 | ---- Uncomment the following library declaration if instantiating |
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| 28 | ---- any Xilinx primitives in this code. |
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| 29 | --library UNISIM; |
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| 30 | --use UNISIM.VComponents.all; |
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| 31 | entity Scheduler2_2 is |
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| 32 | Port ( Request : in STD_LOGIC_VECTOR (4 downto 1); |
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| 33 | Fifo_full : in STD_LOGIC_VECTOR (2 downto 1); |
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| 34 | clk : in STD_LOGIC; |
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| 35 | reset : in STD_LOGIC; |
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| 36 | priority_rotation : in STD_LOGIC_VECTOR (2 downto 1); |
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| 37 | port_grant : out STD_LOGIC_VECTOR (4 downto 1)); |
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| 38 | end Scheduler2_2; |
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| 39 | |
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| 40 | architecture Behavioral of Scheduler2_2 is |
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| 41 | --Declaration du types |
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| 42 | --tableau de signaux de connexion des cellules arbitres |
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| 43 | TYPE C_Bar_Signal_Array IS ARRAY(3 downto 1) of STD_LOGIC_VECTOR(2 downto 1); |
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| 44 | -- declaration du composant cellule d'arbitrage |
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| 45 | Component Arbiter |
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| 46 | PORT (P, Fifo_full,Request, West,North : in STD_LOGIC; |
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| 47 | Grant,East,South : out STD_LOGIC ); |
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| 48 | End Component;--Signaux de connexion des cellues |
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| 49 | SIGNAL south_2_north : C_Bar_Signal_Array; -- connexion south north |
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| 50 | SIGNAL east_2_west : C_Bar_Signal_Array; -- connexion east west |
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| 51 | SIGNAL Signal_mask : C_Bar_Signal_Array;-- connexion des masques de priorité |
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| 52 | SIGNAL Signal_grant : C_Bar_Signal_Array;-- connexion des signaux de validation |
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| 53 | SIGNAL Signal_priority : STD_LOGIC_VECTOR (3 DOWNTO 1);--signal pour la connection des vecteur de priorité |
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| 54 | SIGNAL High : std_logic;--niveau pour les cellules des extremités nord et ouest |
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| 55 | signal grant_latch : std_logic_vector(4 downto 1); |
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| 56 | signal priority_rotation_en : std_logic; |
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| 57 | signal Grant ,req_grant : std_logic_vector(4 downto 1); |
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| 58 | begin |
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| 59 | |
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| 60 | --validation de la rotation de priorité lorsque aucun port n'emet |
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| 61 | req_grant<=(request and grant_latch); |
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| 62 | priority_rotation_en <= '1' when unsigned(req_grant) = 0 or unsigned(priority_rotation) = 3 else '0'; |
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| 63 | --latch servant qui memorise le signal grant pendant a transmission |
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| 64 | grant_latch_process : process(clk) |
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| 65 | begin |
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| 66 | if rising_edge(clk) then |
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| 67 | if reset = '1' then |
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| 68 | grant_latch <= (others => '0'); |
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| 69 | elsif priority_rotation_en = '1' then |
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| 70 | grant_latch <= Grant; |
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| 71 | end if; |
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| 72 | end if; |
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| 73 | end process; |
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| 74 | port_grant <= grant_latch; |
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| 75 | Grant(1) <= Signal_grant(1)(1) or Signal_grant(3)(1); -- Grant(1,1) |
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| 76 | Grant(2) <= Signal_grant(2)(2) ; -- Grant(1,2) |
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| 77 | Grant(3) <= Signal_grant(2)(1) ; -- Grant(2,1) |
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| 78 | Grant(4) <= Signal_grant(1)(2) or Signal_grant(3)(2); -- Grant(2,2) |
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| 79 | High <= '1'; |
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| 80 | |
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| 81 | ----instantiations des cellules arbitres et interconnection |
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| 82 | |
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| 83 | -------------------------- Diagonale n° 1 |
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| 84 | |
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| 85 | |
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| 86 | Arbiter_1_1 : Arbiter |
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| 87 | |
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| 88 | PORT MAP (Request => Request(1), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(1), |
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| 89 | South => south_2_north(1)(1), East => east_2_west(1)(1) , Grant => Signal_grant(1)(1)); |
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| 90 | |
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| 91 | Arbiter_1_2 : Arbiter |
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| 92 | |
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| 93 | PORT MAP (Request => Request(4), North => High, West => High, P => Signal_priority(3), Fifo_full => Fifo_full(2), |
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| 94 | South => south_2_north(1)(2), East => east_2_west(1)(2) , Grant => Signal_grant(1)(2)); |
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| 95 | |
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| 96 | -------------------------- Diagonale n° 2 |
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| 97 | |
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| 98 | |
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| 99 | Arbiter_2_1 : Arbiter |
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| 100 | |
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| 101 | PORT MAP (Request => Request(3), North => south_2_north(1)(1), West => east_2_west(1)(2), P => Signal_priority(2), Fifo_full => Fifo_full(1), |
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| 102 | South => south_2_north(2)(1), East => east_2_west(2)(1) , Grant => Signal_grant(2)(1)); |
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| 103 | |
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| 104 | Arbiter_2_2 : Arbiter |
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| 105 | |
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| 106 | PORT MAP (Request => Request(2), North => south_2_north(1)(2), West => east_2_west(1)(1), P => Signal_priority(2), Fifo_full => Fifo_full(2), |
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| 107 | South => south_2_north(2)(2), East => east_2_west(2)(2) , Grant => Signal_grant(2)(2)); |
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| 108 | |
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| 109 | -------------------------- Diagonale n° 3 |
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| 110 | |
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| 111 | |
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| 112 | Arbiter_3_1 : Arbiter |
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| 113 | |
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| 114 | PORT MAP (Request => Request(1), North => south_2_north(2)(1), West => east_2_west(2)(2), P => Signal_priority(1), Fifo_full => Fifo_full(1), |
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| 115 | South => south_2_north(3)(1), East => east_2_west(3)(1) , Grant => Signal_grant(3)(1)); |
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| 116 | |
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| 117 | Arbiter_3_2 : Arbiter |
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| 118 | |
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| 119 | PORT MAP (Request => Request(4), North => south_2_north(2)(2), West => east_2_west(2)(1), P => Signal_priority(1), Fifo_full => Fifo_full(2), |
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| 120 | South => south_2_north(3)(2), East => east_2_west(3)(2) , Grant => Signal_grant(3)(2)); |
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| 121 | |
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| 122 | |
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| 123 | --processus permettant de roter la priorité des diagonales à chaque front d'horloge |
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| 124 | -- rotation round robin |
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| 125 | round_robin : process(clk) |
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| 126 | begin |
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| 127 | if rising_edge(clk) then |
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| 128 | if reset ='1' then |
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| 129 | Signal_priority <= "110"; |
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| 130 | elsif priority_rotation_en = '1' then |
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| 131 | case Signal_priority is |
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| 132 | when "110" => Signal_priority <= "011"; |
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| 133 | when "011" => Signal_priority <= "110"; |
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| 134 | when others => Signal_priority <= "110"; |
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| 135 | end case; |
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| 136 | end if; |
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| 137 | end if; |
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| 138 | end process; |
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| 139 | |
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| 140 | end Behavioral; |
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| 141 | |
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