[17] | 1 | ---------------------------------------------------------------------------------- |
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| 2 | -- Company: |
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| 3 | -- Engineer: KIEGAING EMMANUEL GEL EN 5 |
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| 4 | -- |
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| 5 | -- Create Date: 19:56:34 05/06/2011 |
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| 6 | -- Design Name: |
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| 7 | -- Module Name: Sheduler - Behavioral |
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| 8 | -- Project Name: |
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| 9 | -- Target Devices: |
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| 10 | -- Tool versions: |
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| 11 | -- Description: Module de l'ordonnanceur du switch crossbar |
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| 12 | -- l'algorithme utilisé est le DPA (diagonal propagation arbiter) |
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| 13 | -- intencie un scheduler particulier en fonction du nombre de port |
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| 14 | -- Dependencies: |
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| 15 | -- |
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| 16 | -- Revision: 1.0 |
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| 17 | -- reconstruction du dpa |
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| 18 | -- Revision 0.01 - File Created |
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| 19 | -- Additional Comments: |
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| 20 | -- |
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| 21 | ---------------------------------------------------------------------------------- |
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| 22 | library IEEE; |
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| 23 | use IEEE.STD_LOGIC_1164.ALL; |
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| 24 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 25 | use IEEE.STD_LOGIC_UNSIGNED.ALL; |
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| 26 | --use Work.Sheduler_package.all; |
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| 27 | |
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| 28 | ---- Uncomment the following library declaration if instantiating |
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| 29 | ---- any Xilinx primitives in this code. |
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| 30 | --library UNISIM; |
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| 31 | --use UNISIM.VComponents.all; |
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| 32 | |
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| 33 | entity Scheduler is |
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| 34 | generic(number_of_ports : positive := 4); |
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| 35 | Port ( Request : in STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1); |
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| 36 | Fifo_full : in STD_LOGIC_VECTOR (number_of_ports downto 1); |
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| 37 | clk : in STD_LOGIC; |
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| 38 | reset : in STD_LOGIC; |
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| 39 | priority_rotation : in STD_LOGIC_VECTOR (number_of_ports downto 1); |
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| 40 | port_grant : out STD_LOGIC_VECTOR (number_of_ports*number_of_ports downto 1)); |
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| 41 | end Scheduler; |
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| 42 | |
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| 43 | architecture Behavioral of Scheduler is |
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| 44 | -- composants du scheduler |
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| 45 | |
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| 46 | -- composants du scheduler |
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| 47 | |
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| 48 | |
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| 49 | COMPONENT Scheduler2_2 |
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| 50 | PORT( |
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| 51 | Request : IN std_logic_vector(4 downto 1); |
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| 52 | Fifo_full : IN std_logic_vector(2 downto 1); |
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| 53 | clk : IN std_logic; |
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| 54 | reset : IN std_logic; |
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| 55 | port_grant : OUT std_logic_vector(4 downto 1); |
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| 56 | priority_rotation : in STD_LOGIC_VECTOR (2 downto 1) |
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| 57 | ); |
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| 58 | END COMPONENT; |
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| 59 | |
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| 60 | COMPONENT Scheduler3_3 |
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| 61 | PORT( |
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| 62 | Request : IN std_logic_vector(9 downto 1); |
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| 63 | Fifo_full : IN std_logic_vector(3 downto 1); |
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| 64 | clk : IN std_logic; |
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| 65 | reset : IN std_logic; |
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| 66 | port_grant : OUT std_logic_vector(9 downto 1); |
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| 67 | priority_rotation : in STD_LOGIC_VECTOR (3 downto 1) |
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| 68 | ); |
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| 69 | END COMPONENT; |
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| 70 | |
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| 71 | COMPONENT Scheduler4_4 |
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| 72 | PORT( |
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| 73 | Request : IN std_logic_vector(16 downto 1); |
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| 74 | Fifo_full : IN std_logic_vector(4 downto 1); |
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| 75 | clk : IN std_logic; |
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| 76 | reset : IN std_logic; |
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| 77 | port_grant : OUT std_logic_vector(16 downto 1); |
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| 78 | priority_rotation : in STD_LOGIC_VECTOR (4 downto 1) |
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| 79 | ); |
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| 80 | END COMPONENT; |
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| 81 | |
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| 82 | COMPONENT Scheduler5_5 |
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| 83 | PORT( |
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| 84 | Request : IN std_logic_vector(25 downto 1); |
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| 85 | Fifo_full : IN std_logic_vector(5 downto 1); |
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| 86 | clk : IN std_logic; |
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| 87 | reset : IN std_logic; |
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| 88 | port_grant : OUT std_logic_vector(25 downto 1); |
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| 89 | priority_rotation : in STD_LOGIC_VECTOR (5 downto 1) |
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| 90 | ); |
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| 91 | END COMPONENT; |
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| 92 | |
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| 93 | COMPONENT Scheduler6_6 |
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| 94 | PORT( |
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| 95 | Request : IN std_logic_vector(36 downto 1); |
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| 96 | Fifo_full : IN std_logic_vector(6 downto 1); |
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| 97 | clk : IN std_logic; |
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| 98 | reset : IN std_logic; |
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| 99 | port_grant : OUT std_logic_vector(36 downto 1); |
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| 100 | priority_rotation : in STD_LOGIC_VECTOR (6 downto 1) |
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| 101 | ); |
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| 102 | END COMPONENT; |
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| 103 | |
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| 104 | COMPONENT Scheduler7_7 |
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| 105 | PORT( |
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| 106 | Request : IN std_logic_vector(49 downto 1); |
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| 107 | Fifo_full : IN std_logic_vector(7 downto 1); |
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| 108 | clk : IN std_logic; |
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| 109 | reset : IN std_logic; |
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| 110 | port_grant : OUT std_logic_vector(49 downto 1); |
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| 111 | priority_rotation : in STD_LOGIC_VECTOR (7 downto 1) |
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| 112 | ); |
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| 113 | END COMPONENT; |
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| 114 | |
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| 115 | COMPONENT Scheduler8_8 |
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| 116 | PORT( |
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| 117 | Request : IN std_logic_vector(64 downto 1); |
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| 118 | Fifo_full : IN std_logic_vector(8 downto 1); |
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| 119 | clk : IN std_logic; |
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| 120 | reset : IN std_logic; |
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| 121 | port_grant : OUT std_logic_vector(64 downto 1); |
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| 122 | priority_rotation : in STD_LOGIC_VECTOR (8 downto 1) |
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| 123 | ); |
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| 124 | END COMPONENT; |
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| 125 | |
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| 126 | COMPONENT Scheduler9_9 |
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| 127 | PORT( |
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| 128 | Request : IN std_logic_vector(81 downto 1); |
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| 129 | Fifo_full : IN std_logic_vector(9 downto 1); |
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| 130 | clk : IN std_logic; |
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| 131 | reset : IN std_logic; |
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| 132 | port_grant : OUT std_logic_vector(81 downto 1); |
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| 133 | priority_rotation : in STD_LOGIC_VECTOR (9 downto 1) |
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| 134 | ); |
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| 135 | END COMPONENT; |
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| 136 | |
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| 137 | COMPONENT Scheduler10_10 |
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| 138 | PORT( |
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| 139 | Request : IN std_logic_vector(100 downto 1); |
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| 140 | Fifo_full : IN std_logic_vector(10 downto 1); |
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| 141 | clk : IN std_logic; |
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| 142 | reset : IN std_logic; |
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| 143 | port_grant : OUT std_logic_vector(100 downto 1); |
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| 144 | priority_rotation : in STD_LOGIC_VECTOR (10 downto 1) |
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| 145 | ); |
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| 146 | END COMPONENT; |
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| 147 | |
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| 148 | COMPONENT Scheduler11_11 |
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| 149 | PORT( |
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| 150 | Request : IN std_logic_vector(121 downto 1); |
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| 151 | Fifo_full : IN std_logic_vector(11 downto 1); |
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| 152 | clk : IN std_logic; |
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| 153 | reset : IN std_logic; |
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| 154 | port_grant : OUT std_logic_vector(121 downto 1); |
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| 155 | priority_rotation : in STD_LOGIC_VECTOR (11 downto 1) |
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| 156 | ); |
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| 157 | END COMPONENT; |
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| 158 | |
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| 159 | COMPONENT Scheduler12_12 |
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| 160 | PORT( |
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| 161 | Request : IN std_logic_vector(144 downto 1); |
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| 162 | Fifo_full : IN std_logic_vector(12 downto 1); |
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| 163 | clk : IN std_logic; |
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| 164 | reset : IN std_logic; |
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| 165 | port_grant : OUT std_logic_vector(144 downto 1); |
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| 166 | priority_rotation : in STD_LOGIC_VECTOR (12 downto 1) |
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| 167 | ); |
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| 168 | END COMPONENT; |
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| 169 | |
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| 170 | COMPONENT Scheduler13_13 |
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| 171 | PORT( |
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| 172 | Request : IN std_logic_vector(169 downto 1); |
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| 173 | Fifo_full : IN std_logic_vector(13 downto 1); |
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| 174 | clk : IN std_logic; |
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| 175 | reset : IN std_logic; |
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| 176 | port_grant : OUT std_logic_vector(169 downto 1); |
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| 177 | priority_rotation : in STD_LOGIC_VECTOR (13 downto 1) |
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| 178 | ); |
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| 179 | END COMPONENT; |
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| 180 | |
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| 181 | COMPONENT Scheduler14_14 |
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| 182 | PORT( |
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| 183 | Request : IN std_logic_vector(196 downto 1); |
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| 184 | Fifo_full : IN std_logic_vector(14 downto 1); |
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| 185 | clk : IN std_logic; |
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| 186 | reset : IN std_logic; |
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| 187 | port_grant : OUT std_logic_vector(196 downto 1); |
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| 188 | priority_rotation : in STD_LOGIC_VECTOR (14 downto 1) |
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| 189 | ); |
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| 190 | END COMPONENT; |
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| 191 | |
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| 192 | COMPONENT Scheduler15_15 |
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| 193 | PORT( |
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| 194 | Request : IN std_logic_vector(225 downto 1); |
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| 195 | Fifo_full : IN std_logic_vector(15 downto 1); |
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| 196 | clk : IN std_logic; |
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| 197 | reset : IN std_logic; |
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| 198 | port_grant : OUT std_logic_vector(225 downto 1); |
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| 199 | priority_rotation : in STD_LOGIC_VECTOR (15 downto 1) |
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| 200 | ); |
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| 201 | END COMPONENT; |
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| 202 | |
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| 203 | COMPONENT Scheduler16_16 |
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| 204 | PORT( |
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| 205 | Request : IN std_logic_vector(256 downto 1); |
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| 206 | Fifo_full : IN std_logic_vector(16 downto 1); |
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| 207 | clk : IN std_logic; |
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| 208 | reset : IN std_logic; |
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| 209 | port_grant : OUT std_logic_vector(256 downto 1); |
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| 210 | priority_rotation : in STD_LOGIC_VECTOR (16 downto 1) |
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| 211 | ); |
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| 212 | END COMPONENT; |
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| 213 | |
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| 214 | |
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| 215 | -- instanciation des scheduler |
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| 216 | --======================scheduler 2 ports======================= |
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| 217 | |
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| 218 | begin |
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| 219 | |
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| 220 | -- instanciation des scheduler |
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| 221 | --======================scheduler 2 ports======================= |
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| 222 | |
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| 223 | scheduler2x2 : if number_of_ports = 2 generate |
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| 224 | |
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| 225 | Inst_Scheduler2_2 : Scheduler2_2 |
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| 226 | PORT MAP( |
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| 227 | Request => Request, |
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| 228 | Fifo_full => Fifo_full, |
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| 229 | clk => clk , |
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| 230 | reset =>reset, |
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| 231 | priority_rotation =>priority_rotation, |
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| 232 | port_grant =>port_grant); |
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| 233 | end generate scheduler2x2; |
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| 234 | |
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| 235 | --======================scheduler 3 ports======================= |
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| 236 | |
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| 237 | scheduler3x3 : if number_of_ports = 3 generate |
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| 238 | |
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| 239 | Inst_Scheduler3_3 : Scheduler3_3 |
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| 240 | PORT MAP( |
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| 241 | Request => Request, |
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| 242 | Fifo_full => Fifo_full, |
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| 243 | clk => clk , |
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| 244 | reset =>reset, |
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| 245 | priority_rotation =>priority_rotation, |
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| 246 | port_grant =>port_grant); |
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| 247 | end generate scheduler3x3; |
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| 248 | |
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| 249 | --======================scheduler 4 ports======================= |
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| 250 | |
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| 251 | scheduler4x4 : if number_of_ports = 4 generate |
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| 252 | |
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| 253 | Inst_Scheduler4_4 : Scheduler4_4 |
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| 254 | PORT MAP( |
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| 255 | Request => Request, |
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| 256 | Fifo_full => Fifo_full, |
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| 257 | clk => clk , |
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| 258 | reset =>reset, |
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| 259 | priority_rotation =>priority_rotation, |
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| 260 | port_grant =>port_grant); |
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| 261 | end generate scheduler4x4; |
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| 262 | |
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| 263 | --======================scheduler 5 ports======================= |
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| 264 | |
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| 265 | scheduler5x5 : if number_of_ports = 5 generate |
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| 266 | |
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| 267 | Inst_Scheduler5_5 : Scheduler5_5 |
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| 268 | PORT MAP( |
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| 269 | Request => Request, |
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| 270 | Fifo_full => Fifo_full, |
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| 271 | clk => clk , |
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| 272 | reset =>reset, |
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| 273 | priority_rotation =>priority_rotation, |
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| 274 | port_grant =>port_grant); |
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| 275 | end generate scheduler5x5; |
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| 276 | |
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| 277 | --======================scheduler 6 ports======================= |
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| 278 | |
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| 279 | scheduler6x6 : if number_of_ports = 6 generate |
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| 280 | |
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| 281 | Inst_Scheduler6_6 : Scheduler6_6 |
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| 282 | PORT MAP( |
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| 283 | Request => Request, |
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| 284 | Fifo_full => Fifo_full, |
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| 285 | clk => clk , |
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| 286 | reset =>reset, |
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| 287 | priority_rotation =>priority_rotation, |
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| 288 | port_grant =>port_grant); |
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| 289 | end generate scheduler6x6; |
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| 290 | |
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| 291 | --======================scheduler 7 ports======================= |
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| 292 | |
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| 293 | scheduler7x7 : if number_of_ports = 7 generate |
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| 294 | |
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| 295 | Inst_Scheduler7_7 : Scheduler7_7 |
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| 296 | PORT MAP( |
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| 297 | Request => Request, |
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| 298 | Fifo_full => Fifo_full, |
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| 299 | clk => clk , |
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| 300 | reset =>reset, |
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| 301 | priority_rotation =>priority_rotation, |
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| 302 | port_grant =>port_grant); |
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| 303 | end generate scheduler7x7; |
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| 304 | |
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| 305 | --======================scheduler 8 ports======================= |
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| 306 | |
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| 307 | scheduler8x8 : if number_of_ports = 8 generate |
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| 308 | |
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| 309 | Inst_Scheduler8_8 : Scheduler8_8 |
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| 310 | PORT MAP( |
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| 311 | Request => Request, |
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| 312 | Fifo_full => Fifo_full, |
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| 313 | clk => clk , |
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| 314 | reset =>reset, |
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| 315 | priority_rotation =>priority_rotation, |
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| 316 | port_grant =>port_grant); |
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| 317 | end generate scheduler8x8; |
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| 318 | |
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| 319 | --======================scheduler 9 ports======================= |
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| 320 | |
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| 321 | scheduler9x9 : if number_of_ports = 9 generate |
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| 322 | |
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| 323 | Inst_Scheduler9_9 : Scheduler9_9 |
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| 324 | PORT MAP( |
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| 325 | Request => Request, |
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| 326 | Fifo_full => Fifo_full, |
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| 327 | clk => clk , |
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| 328 | reset =>reset, |
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| 329 | priority_rotation =>priority_rotation, |
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| 330 | port_grant =>port_grant); |
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| 331 | end generate scheduler9x9; |
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| 332 | |
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| 333 | --======================scheduler 10 ports======================= |
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| 334 | |
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| 335 | scheduler10x10 : if number_of_ports = 10 generate |
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| 336 | |
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| 337 | Inst_Scheduler10_10 : Scheduler10_10 |
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| 338 | PORT MAP( |
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| 339 | Request => Request, |
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| 340 | Fifo_full => Fifo_full, |
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| 341 | clk => clk , |
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| 342 | reset =>reset, |
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| 343 | priority_rotation =>priority_rotation, |
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| 344 | port_grant =>port_grant); |
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| 345 | end generate scheduler10x10; |
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| 346 | |
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| 347 | --======================scheduler 11 ports======================= |
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| 348 | |
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| 349 | scheduler11x11 : if number_of_ports = 11 generate |
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| 350 | |
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| 351 | Inst_Scheduler11_11 : Scheduler11_11 |
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| 352 | PORT MAP( |
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| 353 | Request => Request, |
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| 354 | Fifo_full => Fifo_full, |
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| 355 | clk => clk , |
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| 356 | reset =>reset, |
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| 357 | priority_rotation =>priority_rotation, |
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| 358 | port_grant =>port_grant); |
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| 359 | end generate scheduler11x11; |
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| 360 | |
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| 361 | --======================scheduler 12 ports======================= |
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| 362 | |
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| 363 | scheduler12x12 : if number_of_ports = 12 generate |
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| 364 | |
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| 365 | Inst_Scheduler12_12 : Scheduler12_12 |
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| 366 | PORT MAP( |
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| 367 | Request => Request, |
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| 368 | Fifo_full => Fifo_full, |
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| 369 | clk => clk , |
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| 370 | reset =>reset, |
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| 371 | priority_rotation =>priority_rotation, |
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| 372 | port_grant =>port_grant); |
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| 373 | end generate scheduler12x12; |
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| 374 | |
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| 375 | --======================scheduler 13 ports======================= |
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| 376 | |
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| 377 | scheduler13x13 : if number_of_ports = 13 generate |
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| 378 | |
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| 379 | Inst_Scheduler13_13 : Scheduler13_13 |
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| 380 | PORT MAP( |
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| 381 | Request => Request, |
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| 382 | Fifo_full => Fifo_full, |
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| 383 | clk => clk , |
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| 384 | reset =>reset, |
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| 385 | priority_rotation =>priority_rotation, |
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| 386 | port_grant =>port_grant); |
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| 387 | end generate scheduler13x13; |
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| 388 | |
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| 389 | --======================scheduler 14 ports======================= |
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| 390 | |
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| 391 | scheduler14x14 : if number_of_ports = 14 generate |
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| 392 | |
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| 393 | Inst_Scheduler14_14 : Scheduler14_14 |
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| 394 | PORT MAP( |
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| 395 | Request => Request, |
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| 396 | Fifo_full => Fifo_full, |
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| 397 | clk => clk , |
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| 398 | reset =>reset, |
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| 399 | priority_rotation =>priority_rotation, |
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| 400 | port_grant =>port_grant); |
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| 401 | end generate scheduler14x14; |
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| 402 | |
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| 403 | --======================scheduler 15 ports======================= |
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| 404 | |
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| 405 | scheduler15x15 : if number_of_ports = 15 generate |
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| 406 | |
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| 407 | Inst_Scheduler15_15 : Scheduler15_15 |
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| 408 | PORT MAP( |
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| 409 | Request => Request, |
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| 410 | Fifo_full => Fifo_full, |
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| 411 | clk => clk , |
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| 412 | reset =>reset, |
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| 413 | priority_rotation =>priority_rotation, |
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| 414 | port_grant =>port_grant); |
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| 415 | end generate scheduler15x15; |
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| 416 | |
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| 417 | --======================scheduler 16 ports======================= |
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| 418 | |
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| 419 | scheduler16x16 : if number_of_ports = 16 generate |
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| 420 | |
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| 421 | Inst_Scheduler16_16 : Scheduler16_16 |
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| 422 | PORT MAP( |
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| 423 | Request => Request, |
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| 424 | Fifo_full => Fifo_full, |
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| 425 | clk => clk , |
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| 426 | reset =>reset, |
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| 427 | priority_rotation =>priority_rotation, |
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| 428 | port_grant =>port_grant); |
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| 429 | end generate scheduler16x16; |
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| 430 | |
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| 431 | end Behavioral; |
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| 432 | |
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