source: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/_xmsgs/netgen.xmsgs

<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
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<messages>
<msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">SIMPRIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">SIMPRIM</arg> library for correct compilation and simulation. 
</msg>

<msg type="info" file="NetListWriters" num="0" delta="new" >Xilinx recommends running separate simulations to check for setup by specifying the MAX field in the SDF file and for hold by specifying the MIN field in the SDF file. Please refer to Simulator documentation for more details on specifying MIN and MAX field in the SDF.
</msg>

<msg type="info" file="NetListWriters" num="665" delta="old" >For more information on how to pass the SDF switches to the simulator, see your Simulator tool documentation.
</msg>

</messages>