source: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/iseconfig/SWITCH_GENERIQUE.xreport @ 20

Last change on this file since 20 was 20, checked in by rolagamo, 12 years ago
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1<?xml version='1.0' encoding='UTF-8'?>
2<report-views version="1.7" >
3 <header>
4  <DateModified>2011-11-19T23:52:40</DateModified>
5  <ModuleName>SWITCH_GEN</ModuleName>
6  <SummaryTimeStamp>2011-11-19T23:36:21</SummaryTimeStamp>
7  <DateInitialized>2011-11-19T23:52:40</DateInitialized>
8  <ImplementationReportsDirectory>C:/Core MPI/SWITCH_GENERIC_16_16\</ImplementationReportsDirectory>
9  <SavedFilePath>C:/Core MPI/SWITCH_GENERIC_16_16/iseconfig/SWITCH_GENERIQUE.xreport</SavedFilePath>
10  <EnableMessageFiltering>false</EnableMessageFiltering>
11 </header>
12 <body>
13  <viewgroup label="Design Overview" >
14   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="SWITCH_GEN_summary.html" label="Summary" >
15    <toc-item title="Design Overview" target="Design Overview" />
16    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
17    <toc-item title="Performance Summary" target="Performance Summary" />
18    <toc-item title="Failing Constraints" target="Failing Constraints" />
19    <toc-item title="Detailed Reports" target="Detailed Reports" />
20   </view>
21   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="HTML" file="SWITCH_GEN_partitions.html" label="Partition Report" >
22    <toc-item title="Detailed Reports" target="Detailed Reports" />
23   </view>
24   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SWITCH_GEN_map.xrpt" label="IOB Properties" />
25   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SWITCH_GEN_map.xrpt" label="Control Set Information" />
26   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="SWITCH_GEN_map.xrpt" label="Module Level Utilization" />
27   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="SWITCH_GEN.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
28   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="SWITCH_GEN_par.xrpt" label="Pinout Report" />
29   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="SWITCH_GEN_par.xrpt" label="Clock Report" />
30   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="SWITCH_GEN.twx" label="Static Timing" />
31   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/fit/report.htm" label="CPLD Fitter Report" />
32   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SWITCH_GEN_html/tim/report.htm" label="CPLD Timing Report" />
33  </viewgroup>
34  <viewgroup label="XPS Errors and Warnings" >
35   <view program="platgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/platgen.xmsgs" label="Platgen Messages" />
36   <view program="libgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/libgen.xmsgs" label="Libgen Messages" />
37   <view program="simgen" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/simgen.xmsgs" label="Simgen Messages" />
38   <view program="bitinit" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
39  </viewgroup>
40  <viewgroup label="XPS Reports" >
41   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../platgen.log" label="Platgen Log File" />
42   <view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../libgen.log" label="Libgen Log File" />
43   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../simgen.log" label="Simgen Log File" />
44   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="../bitinit.log" label="BitInit Log File" />
45  </viewgroup>
46  <viewgroup label="Errors and Warnings" >
47   <view inputState="Unknown" program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
48   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
49   <view inputState="Synthesized" program="ngdbuild" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
50   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
51   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
52   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
53   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
54   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
55   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
56   <view inputState="Current" program="implementation" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Current Messages" />
57   <view inputState="Current" program="fitting" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Current Messages (CPLD)" />
58  </viewgroup>
59  <viewgroup label="Detailed Reports" >
60   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="SWITCH_GEN.syr" label="Synthesis Report" >
61    <toc-item title="Top of Report" target="Release" />
62    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
63    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
64    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
65    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
66    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
67    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " />
68    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
69    <toc-item title="Partition Report" target="   Partition Report     " />
70    <toc-item title="Final Report" target="   Final Report   " />
71   </view>
72   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.srr" label="Synplify Report" />
73   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.prec_log" label="Precision Report" />
74   <view inputState="Synthesized" program="ngdbuild" type="Report" file="SWITCH_GEN.bld" label="Translation Report" >
75    <toc-item title="Top of Report" target="Release" />
76    <toc-item title="Command Line" target="Command Line:" />
77    <toc-item title="Partition Status" target="Partition Implementation Status" />
78    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
79   </view>
80   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN_map.mrp" label="Map Report" >
81    <toc-item title="Top of Report" target="Release" />
82    <toc-item title="Section 1: Errors" target="Section 1 - " />
83    <toc-item title="Section 2: Warnings" target="Section 2 - " />
84    <toc-item title="Section 3: Infos" target="Section 3 - " />
85    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 - " />
86    <toc-item title="Section 5: Removed Logic" target="Section 5 - " />
87    <toc-item title="Section 6: IOB Properties" target="Section 6 - " />
88    <toc-item title="Section 7: RPMs" target="Section 7 - " />
89    <toc-item title="Section 8: Guide Report" target="Section 8 - " />
90    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 - " />
91    <toc-item title="Section 10: Modular Design Summary" target="Section 10 - " />
92    <toc-item title="Section 11: Timing Report" target="Section 11 - " />
93    <toc-item title="Section 12: Configuration String Details" target="Section 12 - " />
94    <toc-item title="Section 13: Control Set Information" target="Section 13 - " />
95    <toc-item title="Section 14: Utilization by Hierarchy" target="Section 14 - " />
96   </view>
97   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.par" label="Place and Route Report" >
98    <toc-item title="Top of Report" target="Release" />
99    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
100    <toc-item title="Router Information" target="Starting Router" />
101    <toc-item title="Partition Status" target="Partition Implementation Status" />
102    <toc-item title="Clock Report" target="Generating Clock Report" />
103    <toc-item title="Timing Results" target="Timing Score:" />
104    <toc-item title="Final Summary" target="Peak Memory Usage:" />
105   </view>
106   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.twr" label="Post-PAR Static Timing Report" >
107    <toc-item title="Top of Report" target="Release" />
108    <toc-item title="Data Sheet Report" target="Data Sheet" />
109    <toc-item title="Timing Summary" target="Timing summary:" />
110   </view>
111   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.rpt" label="CPLD Fitter Report (Text)" >
112    <toc-item title="Top of Report" target="cpldfit:" />
113    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
114    <toc-item title="Pin Resources" target="** Pin Resources **" />
115    <toc-item title="Global Resources" target="** Global Control Resources **" />
116   </view>
117   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="SWITCH_GEN.tim" label="CPLD Timing Report (Text)" >
118    <toc-item title="Top of Report" target="Performance Summary Report" />
119    <toc-item title="Performance Summary" target="Performance Summary:" />
120   </view>
121   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="SWITCH_GEN.pwr" label="Power Report" >
122    <toc-item title="Top of Report" target="Release" />
123    <toc-item title="Power summary" target="Power summary" />
124    <toc-item title="Thermal summary" target="Thermal summary" />
125   </view>
126   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="SWITCH_GEN.bgn" label="Bitgen Report" >
127    <toc-item title="Top of Report" target="Release" />
128    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
129    <toc-item title="Final Summary" target="DRC detected" />
130   </view>
131  </viewgroup>
132  <viewgroup label="Secondary Reports" >
133   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
134   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/SWITCH_GEN_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
135    <toc-item title="Top of Report" target="Release" />
136   </view>
137   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/SWITCH_GEN_translate.nlf" label="Post-Translate Simulation Model Report" >
138    <toc-item title="Top of Report" target="Release" />
139   </view>
140   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
141   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN_map.map" label="Map Log File" >
142    <toc-item title="Top of Report" target="Release" />
143    <toc-item title="Design Information" target="Design Information" />
144    <toc-item title="Design Summary" target="Design Summary" />
145   </view>
146   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
147   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_preroute.twr" label="Post-Map Static Timing Report" />
148   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/SWITCH_GEN_map.nlf" label="Post-Map Simulation Model Report" />
149   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_map.psr" label="Physical Synthesis Report" />
150   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SWITCH_GEN_pad.txt" label="Pad Report" >
151    <toc-item title="Top of Report" target="Release" />
152   </view>
153   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SWITCH_GEN.unroutes" label="Unroutes Report" >
154    <toc-item title="Top of Report" target="Release" />
155   </view>
156   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.grf" label="Guide Results Report" />
157   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.dly" label="Asynchronous Delay Report" />
158   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.clk_rgn" label="Clock Region Report" />
159   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
160   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/SWITCH_GEN_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
161   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN_sta.nlf" label="Primetime Netlist Report" >
162    <toc-item title="Top of Report" target="Release" />
163   </view>
164   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.ibs" label="IBIS Model" >
165    <toc-item title="Top of Report" target="IBIS Models for" />
166    <toc-item title="Component" target="Component " />
167   </view>
168   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lck" label="Back-annotate Pin Report" >
169    <toc-item title="Top of Report" target="pin2ucf Report File" />
170    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
171   </view>
172   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SWITCH_GEN.lpc" label="Locked Pin Constraints" >
173    <toc-item title="Top of Report" target="top.lpc" />
174    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
175   </view>
176   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/SWITCH_GEN_timesim.nlf" label="Post-Fit Simulation Model Report" />
177   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
178   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
179  </viewgroup>
180 </body>
181</report-views>
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