[17] | 1 | -- GENERATEUR DE STIMILUS POUR LE TEST DU SWITCH CROSSBAR |
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| 2 | |
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| 3 | library ieee; |
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| 4 | use ieee.std_logic_1164.all; |
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| 5 | use ieee.std_logic_unsigned.all; |
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| 6 | use IEEE.STD_LOGIC_ARITH.ALL; |
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| 7 | |
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| 8 | entity stimuli45 is |
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| 9 | port (clk : in std_logic; |
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| 10 | reset : in std_logic; |
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| 11 | wr_en : out std_logic; |
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| 12 | data : out std_logic_vector(7 downto 0)); |
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| 13 | end stimuli45; |
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| 14 | |
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| 15 | architecture behavioral of stimuli45 is |
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| 16 | type rom_type is array (0 to 69) of std_logic_vector (7 downto 0); |
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| 17 | signal ROM : rom_type:= ( |
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| 18 | X"55", X"28", X"00" ,X"01" ,X"02" ,X"03" , |
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| 19 | X"04" ,X"05" ,X"06" ,X"07" ,X"08" ,X"09" , |
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| 20 | X"0a" ,X"0b" ,X"0c" ,X"0d" ,X"0e" ,X"0f" , |
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| 21 | X"10" ,X"11" ,X"12" ,X"13" ,X"14" ,X"15" , |
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| 22 | X"16" ,X"17" ,X"18" ,X"19" ,X"1a" ,X"1b" , |
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| 23 | X"1c" ,X"1d" ,X"1e" ,X"1f" ,X"20" ,X"21" , |
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| 24 | X"22" ,X"23" ,X"24" ,X"25" ,X"52", X"1e", |
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| 25 | X"00" ,X"01" ,X"02" ,X"03" ,X"04" ,X"05" , |
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| 26 | X"06" ,X"07" ,X"08" ,X"09" ,X"0a" ,X"0b" , |
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| 27 | X"0c" ,X"0d" ,X"0e" ,X"0f" ,X"10" ,X"11" , |
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| 28 | X"12" ,X"13" ,X"14" ,X"15" ,X"16" ,X"17" , |
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| 29 | X"18" ,X"19" ,X"1a" ,X"1b" ); |
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| 30 | |
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| 31 | constant max_address : std_logic_vector(6 downto 0) :="1000101"; |
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| 32 | signal address_counter : std_logic_vector(6 downto 0) := (others => '0'); |
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| 33 | begin |
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| 34 | |
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| 35 | data <= ROM(conv_integer(address_counter)); |
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| 36 | process (clk) |
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| 37 | begin |
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| 38 | if rising_edge(clk) then |
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| 39 | if reset = '1' then |
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| 40 | wr_en <='1'; |
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| 41 | address_counter <= (others=>'0'); |
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| 42 | elsif address_counter < max_address then |
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| 43 | wr_en <='1'; |
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| 44 | address_counter <= address_counter +1; |
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| 45 | else |
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| 46 | wr_en <='0'; |
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| 47 | end if; |
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| 48 | end if; |
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| 49 | end process; |
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| 50 | end behavioral; |
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