source: PROJECT_CORE_MPI/SWITCH_GEN/TRUNK/test_xbar_8x8.vhd

Last change on this file was 22, checked in by rolagamo, 14 years ago
File size: 20.5 KB
Line 
1--------------------------------------------------------------------------------
2-- Company:
3-- Engineer: GAMOM NGOUNOU
4--
5-- Create Date: 19:03:05 07/11/2011
6-- Design Name:
7-- Module Name: C:/Xilinx/SWITCH_GENERIC_16_16/test_xbar_8x8.vhd
8-- Project Name: GENERIC_16_16
9-- Target Device:
10-- Tool versions:
11-- Description:
12--
13-- VHDL Test Bench Created by ISE for module: SWITCH_GENERIQUE
14--
15-- Dependencies:
16--
17-- Revision:
18-- Revision 0.01 - File Created
19-- Additional Comments:
20--
21-- Notes:
22-- This testbench has been automatically generated using types std_logic and
23-- std_logic_vector for the ports of the unit under test. Xilinx recommends
24-- that these types always be used for the top-level I/O of a design in order
25-- to guarantee that the testbench will bind correctly to the post-implementation
26-- simulation model.
27--------------------------------------------------------------------------------
28LIBRARY ieee;
29USE ieee.std_logic_1164.ALL;
30--use IEEE.std_logic_textio.ALL;
31-- Uncomment the following library declaration if using
32-- arithmetic functions with Signed or Unsigned values
33USE ieee.numeric_std.ALL;
34use work.Coretypes.all;
35
36
37ENTITY test_xbar_8x8 IS
38END test_xbar_8x8;
39
40ARCHITECTURE behavior OF test_xbar_8x8 IS
41 CONSTANT MAXPORT :natural:=8;
42 -- Component Declaration for the Unit Under Test (UUT)
43
44 COMPONENT SWITCH_GEN
45 GENERIC (number_of_ports : positive := MAXPORT);
46 PORT(
47 clk : IN std_logic;
48 reset : IN std_logic;
49
50 Port_in : in typ_portIO(1 to MAXPORT) ;
51 Port_out : out typ_portIO(1 to MAXPORT);
52
53 cmd_in_en : IN std_logic_vector(MAXPORT downto 1);
54 data_in_en : IN std_logic_vector(MAXPORT downto 1);
55 data_out_en : IN std_logic_vector(MAXPORT downto 1);
56 fifo_in_full : OUT std_logic_vector(MAXPORT downto 1);
57 fifo_in_empty : OUT std_logic_vector(MAXPORT downto 1);
58 data_available : OUT std_logic_vector(MAXPORT downto 1)
59
60 );
61 END COMPONENT;
62 COMPONENT Stimport5
63 port (
64 clk : in std_logic;
65 reset : in std_logic;
66 clk_en : in std_logic;
67 wr_en : out std_logic;
68 data : out std_logic_vector (7 downto 0)
69 );
70
71 END COMPONENT;
72 type naturel is array (natural range <>) of natural range 0 to 511;
73 type typ_send is (s_head,s_len,s_len2,s_data,s_end);
74 type typ_receiv is (r_wait,r_head,r_dlen,r_glen,r_start,r_end);
75 type typ_cmd is (cmdstart,cmdpost,cmdpostidle,cmdread,cmdlen,cmdglen,cmddata,cmdend,cmdtimeout);
76
77 signal etsnd1,etsnd2,etsnd3 : typ_send;
78 signal etrec:typ_receiv; --pour la machine à état de réception
79 signal etcmd :typ_cmd; --pour la machine à état de commande
80 --Inputs
81 signal PortIn : Typ_portio (1 to MAXPORT);
82 --Outputs
83 signal portOut : Typ_portio(1 to maxport);
84
85 signal data_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
86 signal cmd_in_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
87 signal data_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
88 signal rdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
89 signal rcount : naturel(1 to MAXPORT) ;
90
91 signal cdata_out_en : std_logic_vector(MAXPORT downto 1) := (others => '0');
92 signal clk : std_logic := '0';
93 signal reset : std_logic := '0';
94 signal din1,din2,din3,din4: std_logic_vector(MAXPORT downto 1):= (others => '0');
95 --signaux utiliser pour la mise à jour des MAE
96 signal sdestport,rdestport,rorigport:natural range 0 to 15;
97 signal csend1,csend2,csend3,csend4:natural;
98 signal sorigport :natural range 0 to 15:=1;
99
100
101 signal fifo_in_full : std_logic_vector(MAXPORT downto 1);
102 signal fifo_in_empty : std_logic_vector(MAXPORT downto 1);
103 signal data_available : std_logic_vector(MAXPORT downto 1);
104
105 -- Clock period definitions
106 constant clk_period : time := 10 ns;
107 -- autres signaux de simulation
108 -- ici nous mettons les signaux permettant de gérer le processus de simulation
109 signal time_out:std_logic_vector(8 downto 1);
110 signal header : std_logic_vector(7 downto 0);
111 signal tosend1,tosend2,tosend3,tosend4 : std_logic_vector(7 downto 0);
112
113BEGIN
114
115 -- Instantiate the Unit Under Test (UUT)
116 uut: SWITCH_GEN generic map (MAXPORT) PORT MAP (
117 Port_In => PortIn,
118 Port_Out =>PortOut,
119
120 --signaux de contrôle de la lecture des ports
121 data_in_en => data_in_en,
122 cmd_in_en =>cmd_in_en,
123 data_out_en => data_out_en,
124 fifo_in_full => fifo_in_full,
125 fifo_in_empty => fifo_in_empty,
126 data_available => data_available,
127 clk => clk,
128 reset => reset
129 );
130--Utilisation de la ROM pour envoyer des stimulis
131--stimport: stimport5 port map (clk,reset,not (fifo_in_full(5)),din3(5),port5_in);
132data_in_en<=din1 or din2 or din3 or din4;
133data_out_en<=rdata_out_en or cdata_out_en;
134 -- Clock process definitions
135 clk_process :process
136 begin
137 clk <= '0';
138 wait for clk_period/2;
139 clk <= '1';
140 wait for clk_period/2;
141 end process;
142
143 init_process:process (reset)
144
145 variable i: natural range 0 to 15;
146 begin
147 if reset='1' then
148 for i in 1 to maxport
149 loop
150 --Portin(i)<=(others=>'0');
151end loop ;
152end if ;
153end process init_process;
154 psend1:process(clk,reset)
155 --génération des paquets à partir du premier port
156 variable pactype :natural range 0 to 15;
157 variable origport,destport : natural range 0 to 15;
158 variable datalen,i,i_pair : natural range 0 to 255;
159
160
161
162 begin
163 if reset='1' then
164 etsnd1<=s_head;
165
166 else --reset ='0'
167 origport:=6;
168 if rising_edge(clk) then -- le process s'exécute sur chaque front
169 -- montant de l'horloge
170 case etsnd1 is
171 when s_head => -- construction et envoie de l'en-tête
172 pactype:=5;-- fonction put
173 destport:=6; -- le port de destination
174 datalen :=4;
175 header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
176 tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
177 din1(origport)<='1'; -- en fait data_in_en(origport)
178 i:=1;i_pair:=i /2;
179 etsnd1<=s_len; -- passer à l'état suivant
180 --port1_in<=tosend1;
181 when s_len =>
182 --tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
183 tosend1<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
184
185 din1(origport)<='1';
186
187 --port1_in<=tosend1; --copie directe sur le port
188 etsnd1<=s_len2;
189 when s_len2 =>
190 tosend1<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
191 din1(origport)<='1';
192
193 --port1_in<=tosend1; --copie directe sur le port
194 etsnd1<=s_data;
195 when s_data =>
196
197 if (fifo_in_full(origport)='0') then
198 din1(origport)<='1';
199 i_pair:=i_pair *2;
200 if i=i_pair then -- modulo
201 tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
202 --port1_in<="00001101"; --origport=1
203 else
204 --tosend1<="00001111";
205 tosend1<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
206 --port1_in<="00001111"; --origport=1
207 end if;
208 i:=i+1;i_pair:=i / 2;
209 if i>datalen then
210 etsnd1<=s_end;
211 din1(origport)<='0';
212 end if;
213 else
214 din1(origport)<='1';
215 end if;
216 when s_end =>
217 tosend1<="--------";
218 din1(origport)<='0';
219 if fifo_in_empty(origport)='1' then
220 etsnd1<=s_head;
221 else
222 etsnd1<=s_end;
223 end if;
224 end case;
225
226 end if;
227
228
229
230 end if; --reset='1'
231 end process psend1;
232
233 Portin(6)<=tosend1 when reset='0';
234 Portin(2)<=tosend2 when reset='0';
235 Portin(4)<=tosend3 when reset='0';
236 Portin(1)<=tosend4 when reset='0';
237 psend2:process(clk,reset)
238 --génération des paquets à partir du premier port
239 variable pactype :natural range 0 to 15;
240 variable origport,destport : natural range 0 to 15;
241 variable datalen,i,i_pair : natural range 0 to 255;
242
243
244
245 begin
246 if reset='1' then
247 etsnd2<=s_head;
248
249 else --reset ='0'
250 origport:=2;
251 if rising_edge(clk) then -- le process s'exécute sur chaque front
252 -- montant de l'horloge
253 case etsnd2 is
254 when s_head => -- construction et envoie de l'en-tête
255 pactype:=5;-- fonction put
256 destport:=2; -- le port de destination
257 datalen :=9;
258 header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
259 tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
260 din2(origport)<='1';
261 i:=1;i_pair:=i /2;
262 etsnd2<=s_len; -- passer à l'état suivant
263
264 when s_len =>
265 --tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
266 tosend2<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
267
268 din2(origport)<='1';
269
270 --port2_in<=tosend2; --copie directe sur le port
271 etsnd2<=s_len2;
272 when s_len2 =>
273 tosend2<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
274 din2(origport)<='1';
275
276 --port1_in<=tosend1; --copie directe sur le port
277 etsnd2<=s_data;
278 when s_data =>
279
280 if (fifo_in_full(origport)='0') then
281 din2(origport)<='1';
282 i_pair:=i_pair * 2;
283 if i=i_pair then -- modulo
284 --tosend2<="00000001";
285 tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
286 --port2_in<="00000001"; --origport=1
287 else
288 --tosend2<="00000010";
289 tosend2<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
290 --port2_in<="00000001"; --origport=1
291 end if;
292 i:=i+1;i_pair:=i / 2;
293 if i>datalen then
294 etsnd2<=s_end;
295 din2(origport)<='0';
296 else
297 din2(origport)<='1';
298 end if;
299 else
300 din2(origport)<='0';
301 end if;
302 when s_end =>
303 tosend2<="--------";
304 din2(origport)<='0';
305 if fifo_in_empty(origport)='1' then
306 etsnd2<=s_head;
307 else
308 etsnd2<=s_end;
309 end if;
310 end case;
311
312 end if;
313
314
315
316 end if; --reset='1'
317 end process psend2;
318
319 psend3:process(clk,reset)
320 --génération des paquets à partir du premier port
321 variable pactype :natural range 0 to 15;
322 variable origport,destport : natural range 0 to 15;
323 variable datalen,i,i_pair : natural range 0 to 255;
324
325
326
327 begin
328 if reset='1' then
329 etsnd3<=s_head;
330
331 else --reset ='0'
332 origport:=4; --attention à régler tosend3 =Portin(....) !!!!!!!
333 if rising_edge(clk) then -- le process s'exécute sur chaque front
334 -- montant de l'horloge
335 case etsnd3 is
336 when s_head => -- construction et envoie de l'en-tête
337 pactype:=5;-- fonction put
338 destport:=MAXPORT; -- le port de destination
339 datalen :=4;
340 --header<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport,4));
341 tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
342 din3(origport)<='1'; -- en fait data_in_en(origport)
343 i:=1;i_pair:=i /2;
344 etsnd3<=s_len; -- passer à l'état suivant
345 --port1_in<=tosend1;
346 when s_len =>
347 --tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
348 din3(origport)<='1';
349 tosend3<=STD_LOGIC_VECTOR(to_unsigned(pactype,4)) & STD_LOGIC_VECTOR(to_unsigned(destport-1,4));
350
351 --port1_in<=tosend1; --copie directe sur le port
352 etsnd3<=s_len2;
353 when s_len2 =>
354 tosend3<=(STD_LOGIC_VECTOR(to_unsigned(datalen+2,8)));
355 din3(origport)<='1';
356
357 --port1_in<=tosend1; --copie directe sur le port
358 etsnd3<=s_data;
359 when s_data =>
360
361 if (fifo_in_full(origport)='0') then
362 din3(origport)<='1';
363 i_pair:=i_pair * 2;
364 if i=i_pair then -- modulo
365 tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
366 --tosend3<="00001100";
367 --port1_in<="00001101"; --origport=1
368 else
369 tosend3<=(STD_LOGIC_VECTOR(to_unsigned(i,8)));
370 --tosend3<="00000110";
371 --port1_in<="00001111"; --origport=1
372 end if;
373 i:=i+1;i_pair:=i / 2;
374 if i>datalen then
375 din3(origport)<='0';
376 etsnd3<=s_end;
377 else
378 din3(origport)<='1';
379 end if;
380 else
381 din3(origport)<='0';
382 end if;
383 when s_end =>
384 tosend3<="--------";
385 din3(origport)<='0';
386 if fifo_in_empty(origport)='1' then
387 etsnd3<=s_head;
388 else
389 etsnd3<=s_end;
390 end if;
391 end case;
392
393 end if;
394
395 end if; --reset='1'
396 end process psend3;
397
398 preceiv:process(clk,reset)
399
400 variable origport,ptype : natural range 0 to 15;
401 variable datalen,dcount ,timeout:natural range 0 to 255;
402 variable destport : natural range 0 to 15:=1;
403 begin
404
405 if reset='1' then
406 etrec<=r_wait;
407 destport:=1;
408 timeout:=0;
409 elsif rising_edge(clk) then
410 case etrec is
411 when r_wait =>
412 if destport=0 then
413 destport:=1;
414 end if;
415 timeout:=0;
416 time_out(destport)<='0';
417 if data_available(destport)='1' and cmd_in_en(destport)='0' then
418 rdata_out_en(destport)<='1';
419 etrec<=r_head;
420 else
421 if destport>=MAXPORT then
422 destport:=1;
423 else
424 destport:=destport+1;
425 end if;
426 etrec<=r_wait;
427 end if;
428 when r_head =>
429
430 ptype:=to_integer(unsigned(portout(destport)(7 downto 4)));
431 origport:=to_integer(unsigned(portout(destport)(3 downto 0)));
432 rdata_out_en(destport)<='1';
433 if ptype=5 then
434 etrec<=r_Dlen; --identification de la signature d'en tête valide
435 else
436 etrec<=r_wait;
437 end if;
438
439
440
441
442
443 when r_Dlen => --positionnement du mot de longueur des données
444 if data_available(destport)='1' then
445
446 rdata_out_en(destport)<='1';
447 etrec<=r_glen;
448 timeout:=0;
449 else
450 timeout:=timeout+1;
451 if timeout>=30 then
452 time_out(destport)<='1';
453 etrec<=r_end; -- données pas prêtes
454 end if;
455
456
457 end if;
458 when r_glen => --lecture effective de la longueur des données
459 if data_available(destport)='1' then
460 datalen:=to_integer(unsigned(portout(destport)(7 downto 0)))-3;
461 rdata_out_en(destport)<='1';
462 etrec<=r_start;
463 dcount:=1; -- initialisation du compteur de reception
464 else
465 timeout:=timeout+1;
466 if timeout>=30 then
467 time_out(destport)<='1';
468 etrec<=r_end; -- données pas prêtes
469 end if;
470
471 end if;
472
473 when r_start =>
474 if data_available(destport)='1' then
475
476 dcount:=dcount+1;
477 assert true report "Donnée lue :"; --& string(unsigned(port4_out(7 downto 0)))
478 rdata_out_en(destport)<='1';
479
480 --severity note;
481 if datalen<=dcount then
482 etrec<=r_end;
483
484 elsif dcount=255 then --dépassement de la capacité
485 etrec<=r_end;
486 end if;
487 else
488 timeout:=timeout+1;
489 if timeout>=30 then
490 time_out(destport)<='1';
491 etrec<=r_end; -- données pas prêtes
492 end if;
493
494
495 end if;
496 when r_end =>
497
498
499 rdata_out_en(destport)<='0';
500 rcount(destport)<=rcount(destport)+1;
501 etrec<=r_wait;
502 if destport>=MAXPORT then -- provoquer le passage au prochain port de réception
503 destport:=1;
504 else
505 destport:=destport+1;
506 end if;
507 end case;
508 end if; --reset='1'
509 end process preceiv;
510
511 pcmd:process(clk,reset)
512
513 variable origport,destport,pid,mport : natural range 0 to 15;
514 variable datalen,dcount ,timeout:natural range 0 to 255;
515 begin
516
517 if reset='1' then
518 etcmd<=cmdstart;
519 destport:=0;
520 timeout:=0;
521 origport:=1;
522 sorigport<=origport;
523 elsif rising_edge(clk) then
524 case etcmd is
525 when cmdstart =>
526 if fifo_in_empty(origport)='1' then
527
528
529
530
531 etcmd<=cmdpost;
532 end if;
533 when cmdpost =>
534 if fifo_in_empty(origport)='1' then
535 ---assignations de l'état
536 --din4(origport)<='1';
537 --tosend4<="00000001"; ---code pour getportid
538 etcmd<=cmdpostidle;
539 end if;
540 when cmdpostidle => --permet juste la prise en compte de la commande
541 if data_available(origport)='1' then
542 etcmd<=cmdread;
543 end if;
544 when cmdread =>
545
546
547 timeout:=0;
548 --time_out(destport)<='0';
549 if data_available(origport)='1' then
550 mport:=to_integer(unsigned(portout(origport)(7 downto 4)));
551 pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1;
552 --cdata_out_en(origport)<='1';
553 if pid=origport then --le port a été bien identifié
554 etcmd<=cmdglen; --
555 else
556 etcmd<=cmdtimeout;
557 end if;
558 else
559-- if destport>=MAXPORT then
560-- destport:=1;
561-- else
562-- destport:=destport+1;
563-- end if;
564 etcmd<=cmdread;
565 end if;
566
567
568 when cmdlen => --positionnement du mot de longueur des données
569 if data_available(origport)='1' then
570
571 --cdata_out_en(origport)<='1';
572 etcmd<=cmdglen;
573 timeout:=0;
574 else
575 timeout:=timeout+1;
576 if timeout>=30 then
577 --time_out(destport)<='1';
578 etcmd<=cmdtimeout; -- données pas prêtes
579 end if;
580
581
582 end if;
583 when cmdglen => --lecture effective de la longueur des données
584 if data_available(origport)='1' then
585 datalen:=to_integer(unsigned(portout(origport)(7 downto 0)))-3;
586
587 etcmd<=cmddata;
588 dcount:=0; -- initialisation du compteur de reception
589 else
590 timeout:=timeout+1;
591 if timeout>=30 then
592 --time_out(destport)<='1';
593 etcmd<=cmdtimeout; -- données pas prêtes
594 end if;
595
596 end if;
597
598 when cmddata =>
599 if data_available(origport)='1' and timeout<30 then
600
601 --cdata_out_en(origport)<='1';
602 mport:=to_integer(unsigned(portout(origport)(7 downto 4)));
603 --attention les ports sont numérotés à partir de 0
604 pid:=to_integer(unsigned(portout(origport)(3 downto 0)))+1;
605
606 --severity note;
607 if Pid=origport then
608 etcmd<=cmdend;
609
610 else --dépassement de la capacité
611
612 timeout:=timeout+1;
613 if timeout>=30 then
614 etcmd<=cmdtimeout;
615 end if;
616
617 end if;
618 else
619
620 if timeout>=30 then
621 time_out(origport)<='1';
622 etcmd<=cmdtimeout; -- données pas prêtes
623 end if;
624 timeout:=timeout+1;
625
626 end if;
627 when cmdend =>
628
629
630 --cdata_out_en(origport)<='0';
631
632-- if origport>=mport then -- provoquer le passage au prochain port de réception
633-- origport:=1;
634-- else
635-- origport:=origport+1;
636-- end if;
637 etcmd<=cmdstart;
638 --cmd_in_en(origport)<='0';
639 when cmdtimeout =>
640 etcmd<=cmdtimeout;
641 --cmd_in_en(origport)<='0';
642 etcmd<=cmdstart;
643 end case;
644 sorigport<=origport;
645 end if; --reset='1'
646
647 end process pcmd;
648
649majetcmd:process (etcmd)
650variable origport : natural:=1;-- =sorigport ;
651 begin
652 case etcmd is
653 when cmdstart =>
654
655 cmd_in_en(origport)<='1';
656
657 when cmdpost =>
658 din4(origport)<='1';
659 tosend4<="00000001"; ---code pour getportid
660 cmd_in_en(origport)<='1';
661 cdata_out_en(origport)<='0';
662 when cmdpostidle =>
663 din4(origport)<='0';
664 cdata_out_en(origport)<=data_available(origport);
665 cmd_in_en(origport)<='1';
666
667 when cmdread =>
668 din4(origport)<='0';
669 cdata_out_en(origport)<=data_available(origport);
670 cmd_in_en(origport)<='1';
671
672 when cmdlen |cmdglen => --positionnement du mot de longueur des données
673
674 din4(origport)<='0';
675 cdata_out_en(origport)<=data_available(origport);
676 cmd_in_en(origport)<='1';
677
678 when cmddata =>
679
680 din4(origport)<='0';
681 cdata_out_en(origport)<=data_available(origport);
682 cmd_in_en(origport)<='1';
683
684
685 when cmdend =>
686
687 din4(origport)<='0';
688 cdata_out_en(origport)<='0';
689 cmd_in_en(origport)<='0';
690
691 when cmdtimeout =>
692 din4(origport)<='0';
693 cdata_out_en(origport)<='0';
694 cmd_in_en(origport)<='0';
695
696 end case;
697
698end process majetcmd ;
699 -- Stimulus process
700 stim_proc: process
701 begin
702 -- hold reset state for 100 ns.
703 reset<='1';
704 wait for 1 ns;
705 reset<='1';
706 wait for clk_period*10;
707 reset<='0';
708 wait;
709 -- insert stimulus here
710
711
712
713
714 end process;
715
716END;
Note: See TracBrowser for help on using the repository browser.