source: PROJECT_SMART_EEG/trunk/hw/sync_sys/audio_codec/audio_codec_hw.tcl @ 84

Last change on this file since 84 was 84, checked in by lambert, 10 years ago

Adding hierarchical subdirectory for every component
File size: 5.3 KB
Line 
1# TCL File Generated by Component Editor 13.1
2# Fri Feb 28 16:58:45 CET 2014
3# DO NOT MODIFY
4
5
6#
7# audio_codec "audio_codec" v1.0
8#  2014.02.28.16:58:45
9#
10#
11
12#
13# request TCL package from ACDS 13.1
14#
15package require -exact qsys 13.1
16
17
18#
19# module audio_codec
20#
21set_module_property DESCRIPTION ""
22set_module_property NAME audio_codec
23set_module_property VERSION 1.0
24set_module_property INTERNAL false
25set_module_property OPAQUE_ADDRESS_MAP true
26set_module_property GROUP smartEEG
27set_module_property AUTHOR ""
28set_module_property DISPLAY_NAME audio_codec
29set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
30set_module_property EDITABLE true
31set_module_property ANALYZE_HDL AUTO
32set_module_property REPORT_TO_TALKBACK false
33set_module_property ALLOW_GREYBOX_GENERATION false
34
35
36#
37# file sets
38#
39add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
40set_fileset_property QUARTUS_SYNTH TOP_LEVEL audio_codec
41set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
42add_fileset_file audio_codec.v VERILOG PATH audio_codec.v TOP_LEVEL_FILE
43
44
45#
46# parameters
47#
48
49
50#
51# display items
52#
53
54
55#
56# connection point clock
57#
58add_interface clock clock end
59set_interface_property clock clockRate 0
60set_interface_property clock ENABLED true
61set_interface_property clock EXPORT_OF ""
62set_interface_property clock PORT_NAME_MAP ""
63set_interface_property clock CMSIS_SVD_VARIABLES ""
64set_interface_property clock SVD_ADDRESS_GROUP ""
65
66add_interface_port clock clk clk Input 1
67
68
69#
70# connection point reset
71#
72add_interface reset reset end
73set_interface_property reset associatedClock clock
74set_interface_property reset synchronousEdges DEASSERT
75set_interface_property reset ENABLED true
76set_interface_property reset EXPORT_OF ""
77set_interface_property reset PORT_NAME_MAP ""
78set_interface_property reset CMSIS_SVD_VARIABLES ""
79set_interface_property reset SVD_ADDRESS_GROUP ""
80
81add_interface_port reset reset reset Input 1
82
83
84#
85# connection point ctrl
86#
87add_interface ctrl avalon end
88set_interface_property ctrl addressUnits WORDS
89set_interface_property ctrl associatedClock clock
90set_interface_property ctrl associatedReset reset
91set_interface_property ctrl bitsPerSymbol 8
92set_interface_property ctrl burstOnBurstBoundariesOnly false
93set_interface_property ctrl burstcountUnits WORDS
94set_interface_property ctrl explicitAddressSpan 0
95set_interface_property ctrl holdTime 0
96set_interface_property ctrl linewrapBursts false
97set_interface_property ctrl maximumPendingReadTransactions 0
98set_interface_property ctrl readLatency 0
99set_interface_property ctrl readWaitTime 1
100set_interface_property ctrl setupTime 0
101set_interface_property ctrl timingUnits Cycles
102set_interface_property ctrl writeWaitTime 0
103set_interface_property ctrl ENABLED true
104set_interface_property ctrl EXPORT_OF ""
105set_interface_property ctrl PORT_NAME_MAP ""
106set_interface_property ctrl CMSIS_SVD_VARIABLES ""
107set_interface_property ctrl SVD_ADDRESS_GROUP ""
108
109add_interface_port ctrl avs_ctrl_address address Input 8
110add_interface_port ctrl avs_ctrl_read read Input 1
111add_interface_port ctrl avs_ctrl_readdata readdata Output 32
112add_interface_port ctrl avs_ctrl_write write Input 1
113add_interface_port ctrl avs_ctrl_writedata writedata Input 32
114add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1
115set_interface_assignment ctrl embeddedsw.configuration.isFlash 0
116set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0
117set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0
118set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0
119
120
121#
122# connection point raw_audio
123#
124add_interface raw_audio avalon_streaming end
125set_interface_property raw_audio associatedClock clock
126set_interface_property raw_audio associatedReset reset
127set_interface_property raw_audio dataBitsPerSymbol 8
128set_interface_property raw_audio errorDescriptor ""
129set_interface_property raw_audio firstSymbolInHighOrderBits true
130set_interface_property raw_audio maxChannel 0
131set_interface_property raw_audio readyLatency 0
132set_interface_property raw_audio ENABLED true
133set_interface_property raw_audio EXPORT_OF ""
134set_interface_property raw_audio PORT_NAME_MAP ""
135set_interface_property raw_audio CMSIS_SVD_VARIABLES ""
136set_interface_property raw_audio SVD_ADDRESS_GROUP ""
137
138add_interface_port raw_audio asi_raw_audio_data data Input 32
139add_interface_port raw_audio asi_raw_audio_ready ready Output 1
140add_interface_port raw_audio asi_raw_audio_valid valid Input 1
141
142
143#
144# connection point comp_audio
145#
146add_interface comp_audio avalon_streaming start
147set_interface_property comp_audio associatedClock clock
148set_interface_property comp_audio associatedReset reset
149set_interface_property comp_audio dataBitsPerSymbol 8
150set_interface_property comp_audio errorDescriptor ""
151set_interface_property comp_audio firstSymbolInHighOrderBits true
152set_interface_property comp_audio maxChannel 0
153set_interface_property comp_audio readyLatency 0
154set_interface_property comp_audio ENABLED true
155set_interface_property comp_audio EXPORT_OF ""
156set_interface_property comp_audio PORT_NAME_MAP ""
157set_interface_property comp_audio CMSIS_SVD_VARIABLES ""
158set_interface_property comp_audio SVD_ADDRESS_GROUP ""
159
160add_interface_port comp_audio aso_comp_audio_data data Output 32
161add_interface_port comp_audio aso_comp_audio_ready ready Input 1
162add_interface_port comp_audio aso_comp_audio_valid valid Output 1
163
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