/******************************************************************** * COPYRIGHT LIP6 2014 *-----------------------------------------------------------------*/ /** * @file exg_codec.v * @brief Performs EXG data Compression/Processing * * This module perfoms recieves raw EXG data from AvalonST sink, perfoms compression/processing of the data * and sends the input raw data and compressed data to stream merger module via AvalonST sources * * @author S. Z. Ahmed * @author L. Lambert * @date Fri. 28 Feb. 2014 * * Revision History * @version V1.0 Fri. 28 Feb. 2014 {Initial Arch.: Template file created with qsys gui} * *******************************************************************/ `timescale 1 ps / 1 ps module exg_codec #( parameter AUTO_CLOCK_CLOCK_RATE = "-1" ) ( input wire clk, // clock.clk input wire reset, // reset.reset input wire [31:0] asi_raw_exg_data, // raw_exg.data output wire asi_raw_exg_ready, // .ready input wire asi_raw_exg_valid, // .valid input wire [7:0] avs_ctrl_address, // ctrl.address input wire avs_ctrl_read, // .read output wire [31:0] avs_ctrl_readdata, // .readdata input wire avs_ctrl_write, // .write input wire [31:0] avs_ctrl_writedata, // .writedata output wire avs_ctrl_waitrequest, // .waitrequest output wire [31:0] aso_raw_exg_data, // raw_exg.data input wire aso_raw_exg_ready, // .ready output wire aso_raw_exg_valid, // .valid output wire [31:0] aso_comp_exg_data, // comp_exg.data input wire aso_comp_exg_ready, // .ready output wire aso_comp_exg_valid // .valid ); // TODO: Auto-generated HDL template assign asi_raw_exg_ready = 1'b0; assign avs_ctrl_waitrequest = 1'b0; assign avs_ctrl_readdata = 32'b00000000000000000000000000000000; assign aso_comp_exg_valid = 1'b0; assign aso_comp_exg_data = 32'b00000000000000000000000000000000; endmodule