# TCL File Generated by Component Editor 13.1 # Mon Mar 03 15:32:05 CET 2014 # DO NOT MODIFY # # exg_codec "exg_codec" v1.0 # 2014.03.03.15:32:05 # # # # request TCL package from ACDS 13.1 # package require -exact qsys 13.1 # # module exg_codec # set_module_property DESCRIPTION "" set_module_property NAME exg_codec set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP smartEEG set_module_property AUTHOR "" set_module_property DISPLAY_NAME exg_codec set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL exg_codec set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file exg_codec.v VERILOG PATH exg_codec.v TOP_LEVEL_FILE add_fileset SIM_VERILOG SIM_VERILOG "" "" set_fileset_property SIM_VERILOG TOP_LEVEL exg_codec set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file exg_codec.v VERILOG PATH exg_codec.v # # parameters # add_parameter AUTO_CLOCK_CLOCK_RATE STRING -1 set_parameter_property AUTO_CLOCK_CLOCK_RATE DEFAULT_VALUE -1 set_parameter_property AUTO_CLOCK_CLOCK_RATE DISPLAY_NAME AUTO_CLOCK_CLOCK_RATE set_parameter_property AUTO_CLOCK_CLOCK_RATE TYPE STRING set_parameter_property AUTO_CLOCK_CLOCK_RATE UNITS None set_parameter_property AUTO_CLOCK_CLOCK_RATE HDL_PARAMETER true # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point reset # add_interface reset reset end set_interface_property reset associatedClock clock set_interface_property reset synchronousEdges DEASSERT set_interface_property reset ENABLED true set_interface_property reset EXPORT_OF "" set_interface_property reset PORT_NAME_MAP "" set_interface_property reset CMSIS_SVD_VARIABLES "" set_interface_property reset SVD_ADDRESS_GROUP "" add_interface_port reset reset reset Input 1 # # connection point ctrl # add_interface ctrl avalon end set_interface_property ctrl addressUnits WORDS set_interface_property ctrl associatedClock clock set_interface_property ctrl associatedReset reset set_interface_property ctrl bitsPerSymbol 8 set_interface_property ctrl burstOnBurstBoundariesOnly false set_interface_property ctrl burstcountUnits WORDS set_interface_property ctrl explicitAddressSpan 0 set_interface_property ctrl holdTime 0 set_interface_property ctrl linewrapBursts false set_interface_property ctrl maximumPendingReadTransactions 0 set_interface_property ctrl readLatency 0 set_interface_property ctrl readWaitTime 1 set_interface_property ctrl setupTime 0 set_interface_property ctrl timingUnits Cycles set_interface_property ctrl writeWaitTime 0 set_interface_property ctrl ENABLED true set_interface_property ctrl EXPORT_OF "" set_interface_property ctrl PORT_NAME_MAP "" set_interface_property ctrl CMSIS_SVD_VARIABLES "" set_interface_property ctrl SVD_ADDRESS_GROUP "" add_interface_port ctrl avs_ctrl_address address Input 8 add_interface_port ctrl avs_ctrl_read read Input 1 add_interface_port ctrl avs_ctrl_readdata readdata Output 32 add_interface_port ctrl avs_ctrl_write write Input 1 add_interface_port ctrl avs_ctrl_writedata writedata Input 32 add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 # # connection point raw_exg # add_interface raw_exg avalon_streaming end set_interface_property raw_exg associatedClock clock set_interface_property raw_exg associatedReset reset set_interface_property raw_exg dataBitsPerSymbol 8 set_interface_property raw_exg errorDescriptor "" set_interface_property raw_exg firstSymbolInHighOrderBits true set_interface_property raw_exg maxChannel 0 set_interface_property raw_exg readyLatency 0 set_interface_property raw_exg ENABLED true set_interface_property raw_exg EXPORT_OF "" set_interface_property raw_exg PORT_NAME_MAP "" set_interface_property raw_exg CMSIS_SVD_VARIABLES "" set_interface_property raw_exg SVD_ADDRESS_GROUP "" add_interface_port raw_exg asi_raw_exg_data data Input 32 add_interface_port raw_exg asi_raw_exg_ready ready Output 1 add_interface_port raw_exg asi_raw_exg_valid valid Input 1 # # connection point comp_exg # add_interface comp_exg avalon_streaming start set_interface_property comp_exg associatedClock clock set_interface_property comp_exg associatedReset reset set_interface_property comp_exg dataBitsPerSymbol 8 set_interface_property comp_exg errorDescriptor "" set_interface_property comp_exg firstSymbolInHighOrderBits true set_interface_property comp_exg maxChannel 0 set_interface_property comp_exg readyLatency 0 set_interface_property comp_exg ENABLED true set_interface_property comp_exg EXPORT_OF "" set_interface_property comp_exg PORT_NAME_MAP "" set_interface_property comp_exg CMSIS_SVD_VARIABLES "" set_interface_property comp_exg SVD_ADDRESS_GROUP "" add_interface_port comp_exg aso_comp_exg_data data Output 32 add_interface_port comp_exg aso_comp_exg_ready ready Input 1 add_interface_port comp_exg aso_comp_exg_valid valid Output 1 # # connection point raw_exg_out # add_interface raw_exg_out avalon_streaming start set_interface_property raw_exg_out associatedClock clock set_interface_property raw_exg_out associatedReset reset set_interface_property raw_exg_out dataBitsPerSymbol 8 set_interface_property raw_exg_out errorDescriptor "" set_interface_property raw_exg_out firstSymbolInHighOrderBits true set_interface_property raw_exg_out maxChannel 0 set_interface_property raw_exg_out readyLatency 0 set_interface_property raw_exg_out ENABLED true set_interface_property raw_exg_out EXPORT_OF "" set_interface_property raw_exg_out PORT_NAME_MAP "" set_interface_property raw_exg_out CMSIS_SVD_VARIABLES "" set_interface_property raw_exg_out SVD_ADDRESS_GROUP "" add_interface_port raw_exg_out aso_raw_exg_data data Output 32 add_interface_port raw_exg_out aso_raw_exg_ready ready Input 1 add_interface_port raw_exg_out aso_raw_exg_valid valid Output 1