# TCL File Generated by Component Editor 13.1 # Fri Feb 28 17:27:39 CET 2014 # DO NOT MODIFY # # frame_grabber "frame_grabber" v1.0 # 2014.02.28.17:27:39 # # # # request TCL package from ACDS 13.1 # package require -exact qsys 13.1 # # module frame_grabber # set_module_property DESCRIPTION "" set_module_property NAME frame_grabber set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP smartEEG set_module_property AUTHOR "" set_module_property DISPLAY_NAME frame_grabber set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL frame_grabber set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file frame_grabber.v VERILOG PATH frame_grabber.v TOP_LEVEL_FILE # # parameters # # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point reset # add_interface reset reset end set_interface_property reset associatedClock clock set_interface_property reset synchronousEdges DEASSERT set_interface_property reset ENABLED true set_interface_property reset EXPORT_OF "" set_interface_property reset PORT_NAME_MAP "" set_interface_property reset CMSIS_SVD_VARIABLES "" set_interface_property reset SVD_ADDRESS_GROUP "" add_interface_port reset reset reset Input 1 # # connection point ctrl # add_interface ctrl avalon end set_interface_property ctrl addressUnits WORDS set_interface_property ctrl associatedClock clock set_interface_property ctrl associatedReset reset set_interface_property ctrl bitsPerSymbol 8 set_interface_property ctrl burstOnBurstBoundariesOnly false set_interface_property ctrl burstcountUnits WORDS set_interface_property ctrl explicitAddressSpan 0 set_interface_property ctrl holdTime 0 set_interface_property ctrl linewrapBursts false set_interface_property ctrl maximumPendingReadTransactions 0 set_interface_property ctrl readLatency 0 set_interface_property ctrl readWaitTime 1 set_interface_property ctrl setupTime 0 set_interface_property ctrl timingUnits Cycles set_interface_property ctrl writeWaitTime 0 set_interface_property ctrl ENABLED true set_interface_property ctrl EXPORT_OF "" set_interface_property ctrl PORT_NAME_MAP "" set_interface_property ctrl CMSIS_SVD_VARIABLES "" set_interface_property ctrl SVD_ADDRESS_GROUP "" add_interface_port ctrl avs_s0_address address Input 8 add_interface_port ctrl avs_s0_read read Input 1 add_interface_port ctrl avs_s0_readdata readdata Output 32 add_interface_port ctrl avs_s0_write write Input 1 add_interface_port ctrl avs_s0_writedata writedata Input 32 add_interface_port ctrl avs_s0_waitrequest waitrequest Output 1 set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 # # connection point raw_video # add_interface raw_video avalon_streaming start set_interface_property raw_video associatedClock clock set_interface_property raw_video associatedReset reset set_interface_property raw_video dataBitsPerSymbol 8 set_interface_property raw_video errorDescriptor "" set_interface_property raw_video firstSymbolInHighOrderBits true set_interface_property raw_video maxChannel 0 set_interface_property raw_video readyLatency 0 set_interface_property raw_video ENABLED true set_interface_property raw_video EXPORT_OF "" set_interface_property raw_video PORT_NAME_MAP "" set_interface_property raw_video CMSIS_SVD_VARIABLES "" set_interface_property raw_video SVD_ADDRESS_GROUP "" add_interface_port raw_video aso_out0_data data Output 32 add_interface_port raw_video aso_out0_ready ready Input 1 add_interface_port raw_video aso_out0_valid valid Output 1 # # connection point conduit_camera # add_interface conduit_camera conduit end set_interface_property conduit_camera associatedClock clock set_interface_property conduit_camera associatedReset "" set_interface_property conduit_camera ENABLED true set_interface_property conduit_camera EXPORT_OF "" set_interface_property conduit_camera PORT_NAME_MAP "" set_interface_property conduit_camera CMSIS_SVD_VARIABLES "" set_interface_property conduit_camera SVD_ADDRESS_GROUP "" add_interface_port conduit_camera D5M_D export Input 12 add_interface_port conduit_camera D5M_RESETn export Output 1 add_interface_port conduit_camera D5M_FVAL export Input 1 add_interface_port conduit_camera D5M_LVAL export Input 1 add_interface_port conduit_camera D5M_PIXLCLK export Input 1 add_interface_port conduit_camera D5M_SCLK export Output 1 add_interface_port conduit_camera D5M_SDATA export Bidir 1 add_interface_port conduit_camera D5M_STROBE export Input 1 add_interface_port conduit_camera D5M_TRIGGER export Output 1 add_interface_port conduit_camera D5M_XCLKIN export Output 1