source: PROJECT_SMART_EEG/trunk/hw/sync_sys/signal_grabber.v @ 83

// signal_grabber.v

// This file was auto-generated as a prototype implementation of a module
// created in component editor.  It ties off all outputs to ground and
// ignores all inputs.  It needs to be edited to make it do something
// useful.
// 
// This file will not be automatically regenerated.  You should check it in
// to your version control system if you want to keep it.

`timescale 1 ps / 1 ps
module signal_grabber #(
                parameter ctrl_addr_width = 32,
                parameter ctrl_data_width = 32,
                parameter audio_str_width = 32,
                parameter exg_str_width   = 32,
                parameter etis_si_width   = 32
        ) (
                input  wire        clk,                // clock.clk
                input  wire        reset,              // reset.reset
                input  wire [ctrl_addr_width-1:0] avs_ctrl_address,     //  ctrl.address
                input  wire        avs_ctrl_read,        //      .read
                output wire [31:0] avs_ctrl_readdata,    //      .readdata
                input  wire        avs_ctrl_write,       //      .write
                input  wire [31:0] avs_ctrl_writedata,   //      .writedata
                output wire        avs_ctrl_waitrequest, //      .waitrequest
                output wire [31:0] aso_raw_audio_data,      // audio.data
                input  wire        aso_raw_audio_ready,     //      .ready
                output wire        aso_raw_audio_valid,     //      .valid
                output wire [31:0] aso_raw_exg_data,      //   exg.data
                input  wire        aso_raw_exg_ready,     //      .ready
                output wire        aso_raw_exg_valid
        );

        // TODO: Auto-generated HDL template

        assign avs_ctrl_waitrequest = 1'b0;

        assign avs_ctrl_readdata = 32'b00000000000000000000000000000000;

        assign aso_raw_audio_valid = 1'b0;

        assign aso_raw_audio_data = 32'b00000000000000000000000000000000;

        assign aso_raw_exg_valid = 1'b0;

        assign aso_raw_exg_data = 32'b00000000000000000000000000000000;

        assign asi_etis_ready = 1'b0;

endmodule