[83] | 1 | # TCL File Generated by Component Editor 13.1 |
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[87] | 2 | # Mon Mar 03 15:33:43 CET 2014 |
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[83] | 3 | # DO NOT MODIFY |
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| 4 | |
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| 5 | |
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| 6 | # |
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| 7 | # signal_grabber "signal_grabber" v1.0 |
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[87] | 8 | # 2014.03.03.15:33:43 |
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[83] | 9 | # |
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| 10 | # |
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| 11 | |
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| 12 | # |
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| 13 | # request TCL package from ACDS 13.1 |
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| 14 | # |
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| 15 | package require -exact qsys 13.1 |
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| 16 | |
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| 17 | |
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| 18 | # |
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| 19 | # module signal_grabber |
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| 20 | # |
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| 21 | set_module_property DESCRIPTION "" |
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| 22 | set_module_property NAME signal_grabber |
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| 23 | set_module_property VERSION 1.0 |
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| 24 | set_module_property INTERNAL false |
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| 25 | set_module_property OPAQUE_ADDRESS_MAP true |
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| 26 | set_module_property GROUP smartEEG |
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| 27 | set_module_property AUTHOR "" |
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| 28 | set_module_property DISPLAY_NAME signal_grabber |
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| 29 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true |
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| 30 | set_module_property EDITABLE true |
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| 31 | set_module_property ANALYZE_HDL AUTO |
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| 32 | set_module_property REPORT_TO_TALKBACK false |
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| 33 | set_module_property ALLOW_GREYBOX_GENERATION false |
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| 34 | |
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| 35 | |
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| 36 | # |
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| 37 | # file sets |
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| 38 | # |
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| 39 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" |
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| 40 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL signal_grabber |
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| 41 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false |
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| 42 | add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v TOP_LEVEL_FILE |
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| 43 | |
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[87] | 44 | add_fileset SIM_VERILOG SIM_VERILOG "" "" |
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| 45 | set_fileset_property SIM_VERILOG TOP_LEVEL signal_grabber |
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| 46 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false |
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| 47 | add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v |
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[83] | 48 | |
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[87] | 49 | |
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[83] | 50 | # |
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| 51 | # parameters |
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| 52 | # |
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| 53 | add_parameter ctrl_addr_width POSITIVE 32 "" |
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| 54 | set_parameter_property ctrl_addr_width DEFAULT_VALUE 32 |
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| 55 | set_parameter_property ctrl_addr_width DISPLAY_NAME ctrl_addr_width |
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| 56 | set_parameter_property ctrl_addr_width WIDTH "" |
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| 57 | set_parameter_property ctrl_addr_width TYPE POSITIVE |
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| 58 | set_parameter_property ctrl_addr_width UNITS None |
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| 59 | set_parameter_property ctrl_addr_width ALLOWED_RANGES 1:2147483647 |
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| 60 | set_parameter_property ctrl_addr_width DESCRIPTION "" |
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| 61 | set_parameter_property ctrl_addr_width HDL_PARAMETER true |
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| 62 | add_parameter ctrl_data_width POSITIVE 32 "" |
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| 63 | set_parameter_property ctrl_data_width DEFAULT_VALUE 32 |
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| 64 | set_parameter_property ctrl_data_width DISPLAY_NAME ctrl_data_width |
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| 65 | set_parameter_property ctrl_data_width WIDTH "" |
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| 66 | set_parameter_property ctrl_data_width TYPE POSITIVE |
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| 67 | set_parameter_property ctrl_data_width UNITS None |
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| 68 | set_parameter_property ctrl_data_width ALLOWED_RANGES 1:2147483647 |
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| 69 | set_parameter_property ctrl_data_width DESCRIPTION "" |
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| 70 | set_parameter_property ctrl_data_width HDL_PARAMETER true |
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| 71 | add_parameter audio_str_width POSITIVE 32 "" |
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| 72 | set_parameter_property audio_str_width DEFAULT_VALUE 32 |
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| 73 | set_parameter_property audio_str_width DISPLAY_NAME audio_str_width |
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| 74 | set_parameter_property audio_str_width WIDTH "" |
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| 75 | set_parameter_property audio_str_width TYPE POSITIVE |
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| 76 | set_parameter_property audio_str_width UNITS None |
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| 77 | set_parameter_property audio_str_width ALLOWED_RANGES 1:2147483647 |
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| 78 | set_parameter_property audio_str_width DESCRIPTION "" |
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| 79 | set_parameter_property audio_str_width HDL_PARAMETER true |
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| 80 | add_parameter exg_str_width POSITIVE 32 "" |
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| 81 | set_parameter_property exg_str_width DEFAULT_VALUE 32 |
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| 82 | set_parameter_property exg_str_width DISPLAY_NAME exg_str_width |
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| 83 | set_parameter_property exg_str_width WIDTH "" |
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| 84 | set_parameter_property exg_str_width TYPE POSITIVE |
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| 85 | set_parameter_property exg_str_width UNITS None |
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| 86 | set_parameter_property exg_str_width ALLOWED_RANGES 1:2147483647 |
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| 87 | set_parameter_property exg_str_width DESCRIPTION "" |
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| 88 | set_parameter_property exg_str_width HDL_PARAMETER true |
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| 89 | add_parameter etis_si_width POSITIVE 32 "" |
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| 90 | set_parameter_property etis_si_width DEFAULT_VALUE 32 |
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| 91 | set_parameter_property etis_si_width DISPLAY_NAME etis_si_width |
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| 92 | set_parameter_property etis_si_width WIDTH "" |
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| 93 | set_parameter_property etis_si_width TYPE POSITIVE |
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| 94 | set_parameter_property etis_si_width UNITS None |
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| 95 | set_parameter_property etis_si_width ALLOWED_RANGES 1:2147483647 |
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| 96 | set_parameter_property etis_si_width DESCRIPTION "" |
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| 97 | set_parameter_property etis_si_width HDL_PARAMETER true |
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| 98 | |
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| 99 | |
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| 100 | # |
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| 101 | # display items |
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| 102 | # |
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| 103 | |
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| 104 | |
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| 105 | # |
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| 106 | # connection point clock |
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| 107 | # |
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| 108 | add_interface clock clock end |
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| 109 | set_interface_property clock clockRate 0 |
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| 110 | set_interface_property clock ENABLED true |
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| 111 | set_interface_property clock EXPORT_OF "" |
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| 112 | set_interface_property clock PORT_NAME_MAP "" |
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| 113 | set_interface_property clock CMSIS_SVD_VARIABLES "" |
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| 114 | set_interface_property clock SVD_ADDRESS_GROUP "" |
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| 115 | |
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| 116 | add_interface_port clock clk clk Input 1 |
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| 117 | |
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| 118 | |
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| 119 | # |
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| 120 | # connection point reset |
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| 121 | # |
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| 122 | add_interface reset reset end |
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| 123 | set_interface_property reset associatedClock clock |
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| 124 | set_interface_property reset synchronousEdges DEASSERT |
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| 125 | set_interface_property reset ENABLED true |
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| 126 | set_interface_property reset EXPORT_OF "" |
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| 127 | set_interface_property reset PORT_NAME_MAP "" |
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| 128 | set_interface_property reset CMSIS_SVD_VARIABLES "" |
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| 129 | set_interface_property reset SVD_ADDRESS_GROUP "" |
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| 130 | |
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| 131 | add_interface_port reset reset reset Input 1 |
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| 132 | |
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| 133 | |
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| 134 | # |
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| 135 | # connection point ctrl |
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| 136 | # |
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| 137 | add_interface ctrl avalon end |
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| 138 | set_interface_property ctrl addressUnits WORDS |
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| 139 | set_interface_property ctrl associatedClock clock |
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| 140 | set_interface_property ctrl associatedReset reset |
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| 141 | set_interface_property ctrl bitsPerSymbol 8 |
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| 142 | set_interface_property ctrl burstOnBurstBoundariesOnly false |
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| 143 | set_interface_property ctrl burstcountUnits WORDS |
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| 144 | set_interface_property ctrl explicitAddressSpan 0 |
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| 145 | set_interface_property ctrl holdTime 0 |
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| 146 | set_interface_property ctrl linewrapBursts false |
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| 147 | set_interface_property ctrl maximumPendingReadTransactions 0 |
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| 148 | set_interface_property ctrl readLatency 0 |
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| 149 | set_interface_property ctrl readWaitTime 1 |
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| 150 | set_interface_property ctrl setupTime 0 |
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| 151 | set_interface_property ctrl timingUnits Cycles |
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| 152 | set_interface_property ctrl writeWaitTime 0 |
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| 153 | set_interface_property ctrl ENABLED true |
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| 154 | set_interface_property ctrl EXPORT_OF "" |
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| 155 | set_interface_property ctrl PORT_NAME_MAP "" |
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| 156 | set_interface_property ctrl CMSIS_SVD_VARIABLES "" |
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| 157 | set_interface_property ctrl SVD_ADDRESS_GROUP "" |
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| 158 | |
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| 159 | add_interface_port ctrl avs_ctrl_address address Input ctrl_addr_width |
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| 160 | add_interface_port ctrl avs_ctrl_read read Input 1 |
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| 161 | add_interface_port ctrl avs_ctrl_readdata readdata Output 32 |
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| 162 | add_interface_port ctrl avs_ctrl_write write Input 1 |
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| 163 | add_interface_port ctrl avs_ctrl_writedata writedata Input 32 |
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| 164 | add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 |
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| 165 | set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 |
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| 166 | set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 |
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| 167 | set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 |
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| 168 | set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 |
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| 169 | |
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| 170 | |
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| 171 | # |
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| 172 | # connection point raw_audio |
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| 173 | # |
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| 174 | add_interface raw_audio avalon_streaming start |
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| 175 | set_interface_property raw_audio associatedClock clock |
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| 176 | set_interface_property raw_audio associatedReset reset |
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| 177 | set_interface_property raw_audio dataBitsPerSymbol 8 |
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| 178 | set_interface_property raw_audio errorDescriptor "" |
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| 179 | set_interface_property raw_audio firstSymbolInHighOrderBits true |
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| 180 | set_interface_property raw_audio maxChannel 0 |
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| 181 | set_interface_property raw_audio readyLatency 0 |
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| 182 | set_interface_property raw_audio ENABLED true |
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| 183 | set_interface_property raw_audio EXPORT_OF "" |
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| 184 | set_interface_property raw_audio PORT_NAME_MAP "" |
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| 185 | set_interface_property raw_audio CMSIS_SVD_VARIABLES "" |
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| 186 | set_interface_property raw_audio SVD_ADDRESS_GROUP "" |
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| 187 | |
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| 188 | add_interface_port raw_audio aso_raw_audio_data data Output 32 |
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| 189 | add_interface_port raw_audio aso_raw_audio_ready ready Input 1 |
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| 190 | add_interface_port raw_audio aso_raw_audio_valid valid Output 1 |
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| 191 | |
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| 192 | |
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| 193 | # |
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| 194 | # connection point raw_exg |
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| 195 | # |
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| 196 | add_interface raw_exg avalon_streaming start |
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| 197 | set_interface_property raw_exg associatedClock clock |
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| 198 | set_interface_property raw_exg associatedReset reset |
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| 199 | set_interface_property raw_exg dataBitsPerSymbol 8 |
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| 200 | set_interface_property raw_exg errorDescriptor "" |
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| 201 | set_interface_property raw_exg firstSymbolInHighOrderBits true |
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| 202 | set_interface_property raw_exg maxChannel 0 |
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| 203 | set_interface_property raw_exg readyLatency 0 |
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| 204 | set_interface_property raw_exg ENABLED true |
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| 205 | set_interface_property raw_exg EXPORT_OF "" |
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| 206 | set_interface_property raw_exg PORT_NAME_MAP "" |
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| 207 | set_interface_property raw_exg CMSIS_SVD_VARIABLES "" |
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| 208 | set_interface_property raw_exg SVD_ADDRESS_GROUP "" |
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| 209 | |
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| 210 | add_interface_port raw_exg aso_raw_exg_data data Output 32 |
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| 211 | add_interface_port raw_exg aso_raw_exg_ready ready Input 1 |
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| 212 | add_interface_port raw_exg aso_raw_exg_valid valid Output 1 |
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| 213 | |
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