# TCL File Generated by Component Editor 13.1 # Mon Mar 03 15:33:43 CET 2014 # DO NOT MODIFY # # signal_grabber "signal_grabber" v1.0 # 2014.03.03.15:33:43 # # # # request TCL package from ACDS 13.1 # package require -exact qsys 13.1 # # module signal_grabber # set_module_property DESCRIPTION "" set_module_property NAME signal_grabber set_module_property VERSION 1.0 set_module_property INTERNAL false set_module_property OPAQUE_ADDRESS_MAP true set_module_property GROUP smartEEG set_module_property AUTHOR "" set_module_property DISPLAY_NAME signal_grabber set_module_property INSTANTIATE_IN_SYSTEM_MODULE true set_module_property EDITABLE true set_module_property ANALYZE_HDL AUTO set_module_property REPORT_TO_TALKBACK false set_module_property ALLOW_GREYBOX_GENERATION false # # file sets # add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" set_fileset_property QUARTUS_SYNTH TOP_LEVEL signal_grabber set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v TOP_LEVEL_FILE add_fileset SIM_VERILOG SIM_VERILOG "" "" set_fileset_property SIM_VERILOG TOP_LEVEL signal_grabber set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false add_fileset_file signal_grabber.v VERILOG PATH signal_grabber.v # # parameters # add_parameter ctrl_addr_width POSITIVE 32 "" set_parameter_property ctrl_addr_width DEFAULT_VALUE 32 set_parameter_property ctrl_addr_width DISPLAY_NAME ctrl_addr_width set_parameter_property ctrl_addr_width WIDTH "" set_parameter_property ctrl_addr_width TYPE POSITIVE set_parameter_property ctrl_addr_width UNITS None set_parameter_property ctrl_addr_width ALLOWED_RANGES 1:2147483647 set_parameter_property ctrl_addr_width DESCRIPTION "" set_parameter_property ctrl_addr_width HDL_PARAMETER true add_parameter ctrl_data_width POSITIVE 32 "" set_parameter_property ctrl_data_width DEFAULT_VALUE 32 set_parameter_property ctrl_data_width DISPLAY_NAME ctrl_data_width set_parameter_property ctrl_data_width WIDTH "" set_parameter_property ctrl_data_width TYPE POSITIVE set_parameter_property ctrl_data_width UNITS None set_parameter_property ctrl_data_width ALLOWED_RANGES 1:2147483647 set_parameter_property ctrl_data_width DESCRIPTION "" set_parameter_property ctrl_data_width HDL_PARAMETER true add_parameter audio_str_width POSITIVE 32 "" set_parameter_property audio_str_width DEFAULT_VALUE 32 set_parameter_property audio_str_width DISPLAY_NAME audio_str_width set_parameter_property audio_str_width WIDTH "" set_parameter_property audio_str_width TYPE POSITIVE set_parameter_property audio_str_width UNITS None set_parameter_property audio_str_width ALLOWED_RANGES 1:2147483647 set_parameter_property audio_str_width DESCRIPTION "" set_parameter_property audio_str_width HDL_PARAMETER true add_parameter exg_str_width POSITIVE 32 "" set_parameter_property exg_str_width DEFAULT_VALUE 32 set_parameter_property exg_str_width DISPLAY_NAME exg_str_width set_parameter_property exg_str_width WIDTH "" set_parameter_property exg_str_width TYPE POSITIVE set_parameter_property exg_str_width UNITS None set_parameter_property exg_str_width ALLOWED_RANGES 1:2147483647 set_parameter_property exg_str_width DESCRIPTION "" set_parameter_property exg_str_width HDL_PARAMETER true add_parameter etis_si_width POSITIVE 32 "" set_parameter_property etis_si_width DEFAULT_VALUE 32 set_parameter_property etis_si_width DISPLAY_NAME etis_si_width set_parameter_property etis_si_width WIDTH "" set_parameter_property etis_si_width TYPE POSITIVE set_parameter_property etis_si_width UNITS None set_parameter_property etis_si_width ALLOWED_RANGES 1:2147483647 set_parameter_property etis_si_width DESCRIPTION "" set_parameter_property etis_si_width HDL_PARAMETER true # # display items # # # connection point clock # add_interface clock clock end set_interface_property clock clockRate 0 set_interface_property clock ENABLED true set_interface_property clock EXPORT_OF "" set_interface_property clock PORT_NAME_MAP "" set_interface_property clock CMSIS_SVD_VARIABLES "" set_interface_property clock SVD_ADDRESS_GROUP "" add_interface_port clock clk clk Input 1 # # connection point reset # add_interface reset reset end set_interface_property reset associatedClock clock set_interface_property reset synchronousEdges DEASSERT set_interface_property reset ENABLED true set_interface_property reset EXPORT_OF "" set_interface_property reset PORT_NAME_MAP "" set_interface_property reset CMSIS_SVD_VARIABLES "" set_interface_property reset SVD_ADDRESS_GROUP "" add_interface_port reset reset reset Input 1 # # connection point ctrl # add_interface ctrl avalon end set_interface_property ctrl addressUnits WORDS set_interface_property ctrl associatedClock clock set_interface_property ctrl associatedReset reset set_interface_property ctrl bitsPerSymbol 8 set_interface_property ctrl burstOnBurstBoundariesOnly false set_interface_property ctrl burstcountUnits WORDS set_interface_property ctrl explicitAddressSpan 0 set_interface_property ctrl holdTime 0 set_interface_property ctrl linewrapBursts false set_interface_property ctrl maximumPendingReadTransactions 0 set_interface_property ctrl readLatency 0 set_interface_property ctrl readWaitTime 1 set_interface_property ctrl setupTime 0 set_interface_property ctrl timingUnits Cycles set_interface_property ctrl writeWaitTime 0 set_interface_property ctrl ENABLED true set_interface_property ctrl EXPORT_OF "" set_interface_property ctrl PORT_NAME_MAP "" set_interface_property ctrl CMSIS_SVD_VARIABLES "" set_interface_property ctrl SVD_ADDRESS_GROUP "" add_interface_port ctrl avs_ctrl_address address Input ctrl_addr_width add_interface_port ctrl avs_ctrl_read read Input 1 add_interface_port ctrl avs_ctrl_readdata readdata Output 32 add_interface_port ctrl avs_ctrl_write write Input 1 add_interface_port ctrl avs_ctrl_writedata writedata Input 32 add_interface_port ctrl avs_ctrl_waitrequest waitrequest Output 1 set_interface_assignment ctrl embeddedsw.configuration.isFlash 0 set_interface_assignment ctrl embeddedsw.configuration.isMemoryDevice 0 set_interface_assignment ctrl embeddedsw.configuration.isNonVolatileStorage 0 set_interface_assignment ctrl embeddedsw.configuration.isPrintableDevice 0 # # connection point raw_audio # add_interface raw_audio avalon_streaming start set_interface_property raw_audio associatedClock clock set_interface_property raw_audio associatedReset reset set_interface_property raw_audio dataBitsPerSymbol 8 set_interface_property raw_audio errorDescriptor "" set_interface_property raw_audio firstSymbolInHighOrderBits true set_interface_property raw_audio maxChannel 0 set_interface_property raw_audio readyLatency 0 set_interface_property raw_audio ENABLED true set_interface_property raw_audio EXPORT_OF "" set_interface_property raw_audio PORT_NAME_MAP "" set_interface_property raw_audio CMSIS_SVD_VARIABLES "" set_interface_property raw_audio SVD_ADDRESS_GROUP "" add_interface_port raw_audio aso_raw_audio_data data Output 32 add_interface_port raw_audio aso_raw_audio_ready ready Input 1 add_interface_port raw_audio aso_raw_audio_valid valid Output 1 # # connection point raw_exg # add_interface raw_exg avalon_streaming start set_interface_property raw_exg associatedClock clock set_interface_property raw_exg associatedReset reset set_interface_property raw_exg dataBitsPerSymbol 8 set_interface_property raw_exg errorDescriptor "" set_interface_property raw_exg firstSymbolInHighOrderBits true set_interface_property raw_exg maxChannel 0 set_interface_property raw_exg readyLatency 0 set_interface_property raw_exg ENABLED true set_interface_property raw_exg EXPORT_OF "" set_interface_property raw_exg PORT_NAME_MAP "" set_interface_property raw_exg CMSIS_SVD_VARIABLES "" set_interface_property raw_exg SVD_ADDRESS_GROUP "" add_interface_port raw_exg aso_raw_exg_data data Output 32 add_interface_port raw_exg aso_raw_exg_ready ready Input 1 add_interface_port raw_exg aso_raw_exg_valid valid Output 1