source: PROJECT_SMART_EEG/trunk/hw/sync_sys/stream_merger.v @ 83

// stream_merger.v

// This file was auto-generated as a prototype implementation of a module
// created in component editor.  It ties off all outputs to ground and
// ignores all inputs.  It needs to be edited to make it do something
// useful.
// 
// This file will not be automatically regenerated.  You should check it in
// to your version control system if you want to keep it.

`timescale 1 ps / 1 ps
module stream_merger #(
                parameter AUTO_CLOCK_CLOCK_RATE = "-1"
        ) (
                input  wire        clk,                //     clock.clk
                input  wire        reset,              //     reset.reset
                input  wire [7:0]  avs_ctrl_address,     //      ctrl.address
                input  wire        avs_ctrl_read,        //          .read
                output wire [31:0] avs_ctrl_readdata,    //          .readdata
                input  wire        avs_ctrl_write,       //          .write
                input  wire [31:0] avs_ctrl_writedata,   //          .writedata
                output wire        avs_ctrl_waitrequest, //          .waitrequest
                input  wire [31:0] asi_raw_video_data,       // raw_video.data
                output wire        asi_raw_video_ready,      //          .ready
                input  wire        asi_raw_video_valid,       //          .valid
                input  wire [31:0] asi_raw_exg_data,       // raw_exg.data
                output wire        asi_raw_exg_ready,      //          .ready
                input  wire        asi_raw_exg_valid,       //          .valid
                input  wire [31:0] asi_comp_video_data,       // comp_video.data
                output wire        asi_comp_video_ready,      //          .ready
                input  wire        asi_comp_video_valid,       //          .valid
                input  wire [31:0] asi_comp_exg_data,       // comp_exg.data
                output wire        asi_comp_exg_ready,      //          .ready
                input  wire        asi_comp_exg_valid,       //          .valid
                input  wire [31:0] asi_comp_audio_data,       // comp_audio.data
                output wire        asi_comp_audio_ready,      //          .ready
                input  wire        asi_comp_audio_valid       //          .valid
        );

        // TODO: Auto-generated HDL template

        assign avs_ctrl_waitrequest = 1'b0;

        assign avs_ctrl_readdata = 32'b00000000000000000000000000000000;

        assign asi_in0_ready = 1'b0;

endmodule